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Design Considerations in CLBs for Deep Sub-Micron Technologies

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Motivation

As technology scales…

- The effects due to process variations will become more pronounced.
- Regular structures are needed to mitigate these effects.
- Leakage will increase as the VTH are scaled.
- Low leakage architectures will be needed to control stand-by power.

Stack

Regular

Low Leakage

Slow due to RC delay

Current Sensing

Recover performance loss through smaller voltage swings.

Current

Sense

OUT

OUT

CLK

S

S

Pass

Transistor

Stack

Data

Inputs

Program

Bits

Configurable Logic BlockI1

V2

V1

IOFF 0

V1

V2

ION

IBIAS

V = V1 - V2 > 0

ION

IOFF

CLB

V2

V1

ION

IOFF

Sense Amplifier TopologiesConditional

Precharge

Sense

Amplifier

(CP)

Clamped

Bit-Line

Sense

Amplifier

(CBL)

DCVSL-based

Sense Amplifier

(DCVSL-SA)

I1

V2

V1

IOFF 0

V1

V2

ION

IBIAS

V = V1 - V2 > 0

ION

IOFF

V2

V1

CLB

ION

IOFF

Sense Amplifier TopologiesConditional

Precharge

Sense

Amplifier

(CP)

Clamped

Bit-Line

Sense

Amplifier

(CBL)

DCVSL-based

Sense Amplifier

(DCVSL-SA)

I1

V2

V1

IOFF 0

ION

IBIAS

V1

V2

V = V1 - V2 > 0

ION

IOFF

V2

V1

CLB

ION

IOFF

Sense Amplifier TopologiesConditional

Precharge

Sense

Amplifier

(CP)

Clamped

Bit-Line

Sense

Amplifier

(CBL)

DCVSL-based

Sense Amplifier

(DCVSL-SA)

I1

V2

V1

IOFF 0

ION

IBIAS

V = V1 - V2 > 0

V2

V1

ION

IOFF

Sense Amplifier TopologiesConditional

Precharge

Sense

Amplifier

(CP)

V1

V2

ION

IOFF

CLB

Clamped

Bit-Line

Sense

Amplifier

(CBL)

DCVSL-based

Sense Amplifier

(DCVSL-SA)

Leakage Current

CBL

CMOS

CMOS

CP

CBL

TG

DCVSL-SA

DCVSL-SA

TG

CP

EDP and LeakageEDP

Looks too good to be true? It probably is…

Process Variation and Mismatch

ION,min needed

by the sense

amplifier

V should be > 0

for proper sensing

upsize

ION

VSA

CLB

(Stack)

CP

SA

Root

Input

ION

VSA

IOFF

CBL

CP

CBL

DCVSL-SA

DCVSL-SA

CP

Sizing for YieldLeakage Current

EDP

- Yield Target: 99% (Monte Carlo process and mismatch simulations)
- needs to be verified in silicon

Solid line has a 99% yield over all process corners.

Overkill?

The yield increases as VDD increases

Constant Yield LinesCP (Upsized)

CLB: 10x

CP Sense Amp: 2x

EDP CP

Performance

Loss

CP

Dash-dotted line represents a constant Yield Line.

Size of CLB tailored to desired Yield and VDD.

Constant Yield LinesCP (Upsized)

CLB: 10x

CP Sense Amp: 2x

EDP CP

B

99% yield line

A

CP

YieldB = YieldA

Constant Yield Lines

CP (Upsized)

CLB: 10x

CP Sense Amp: 2x

Upsized EDP

EDP CP

B

99% yield line

CP

A

CMOS

CP

TG

YieldB = YieldA

Constant Yield Lines

Upsized EDP

EDP

CBL

DCVSL-SA (Upsized)

CP

B

DCVSL-SA 99% line

CMOS

A

DCVSL-SA

TG

DCVSL-SA

YieldB = YieldA

EDP

(w/o sizing for yield)

EDP

(constant yield)

CBL

CBL

CP

CP

CMOS

CMOS

TG

TG

DCVSL-SA

DCVSL-SA

EDP and YieldHigh Voltage Space

EDP

(constant yield)

CBL

Leakage

Current

CMOS

CP

CBL

CMOS

DCVSL-SA

TG

TG

CP

DCVSL-SA

Summary of Results- DCVSL-SA best performing SA, and competitive with current TG and CMOS implementations.

However…

- More difficult to design
- Analog-like design process
- Less versatile
- Mandatory latch at the output
- DVS
- Higher design risk
- 6 unacceptable

Summary of Results

- DCVSL-SA best performing SA, and competitive with current TG and CMOS implementations.

However…

- More difficult to design
- Analog-like design process
- Less versatile
- Mandatory latch at the output
- DVS
- Higher design risk
- 6 unacceptable

Sense Amplifiers in Future Technologies

- Design of Sense Amplifiers in the future will become more challenging.
- Impact of process variations will become more pronounced
- VDD will continue to scale
- VSA/VDD increases
- VTH/VDD increases
- The useful design space will be limited.
- Low leakage environments
- High voltage, low energy space

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