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### Microwave Oscillator

By

Professor Syed Idris Syed Hassan

Sch of Elect. & Electron Eng

Engineering Campus USM

Nibong Tebal 14300

SPS Penang

One-port negative Oscillator using IMPATT or Gunn diodes

Negative resistance device is usually a biased diode. Oscillation

occurred whence ZL= -Zinwhich implies

Stability of oscillation

Oscillation takes place when the circuit first unstable, i.e Rin +RL < 0 .

Rin depends on current and frequency. Any transient or noise will excite or cause oscillation . The oscillation will become stable when Rin +RL=0 and Xin +XL=0. The stable frequency is fo.

Let’s ZT(I,s)= Zin(I,s)+ZL(s)

Where I current and s=jw is a complex frequency. Then for a small change in current dI and in frequency ds, the Taylor’s series for ZT(I,s) is

Continue (stability)

Use the fact that

Where ds=da+jdw

Therefore

If the transient caused by dI and ds to decay we must have da < 0 when dI>0 so that

Or subst ZT=RT+jXT

Continue ( stability)

For passive load

By substituting ZT=Zin + ZL, the stability equation reduces to

Where Zin = Rin + j Xin

ZL =RL + jXL

Matching diode oscillator

Eg. A negative -resistive diode having Gin=1.25 /40o (Zo=50ohm) at its desired operating point , for 6 GHz . Design a load matching network for one-port of 50 ohm load oscillator.

By plotting ZL in Smith chart then match to 50 ohm as usual. The

50W

FET oscillator

- Choose high degree of unstable device. Typically, common
- source or common gate are used.Often positive feedback to
- enhance instability.
- Draw output stable circle and choose GT for large negative
- resistance (I.e Zin). Then take ZL to match Zin. Choose RL such that RL+Rin < 0, otherwise oscillation will cease.

FET common gate

Design 4GHz oscillator using common gate FET configuration

with 5nH inductor to increase instability. Output port is 50W. S-

parameter for FET with common source configuration are : (Zo=50W) S11= 0.72/-116o, S21=2.6/76o, S12=0.03/57o,S22=0.73/-54o.

5nH

continue

First we have to convert from common source S-parameter

to common gate with series inductor S-parameter. This is

usually done using CAD. The new S-parameter is given by

S11’= 2.18/-35o, S21’=2.75/96o, S12’=1.26/18o,S22’=0.52/155o.

Thus the output stability circle parameters are given as

where

To determine GT

Since S’11>1, thus the stable region is inside the shaded circle.

GT can be choose anywhere in the Smith chart but the main objective Gin should be larger than 1. Let say we choose GT=0.59/-104. Then calculate Gin, thus

Or Zin= -84 - j1.9 W

Then

Using a transmission line to match a resistive load, thus we have a length of 0.241 l and a load of 89.5 W. Using Rin/3 should ensure enough instability for the startup of oscillator. It is easier to implement ZL =90 ohm . The steady -state oscillation frequency will differ from 4Ghz due to the nonlinearity of the transistor

0.346l

For GT matching, we can use open-stub to match 50 ohm. Plot GT and then determine the YT. Moving towards load until meet the crossing point between SWR circle and the unity circle. That the distant between transistor and the stub. Obtain the susceptance and distance towards open circuit.

Towards generator

GL

0.319l

GT

Dielectric resonator

Equivalent series impedance

Where N =coupling factor/turn ratio

Q=R/woL (unloaded resonator)

Ratio of unloaded to external Q is given by

where

RL=2Zo for loaded resistance

= Zo for l/4 transmission line

Continue (Dielectric resonator)

Reflection coefficient looking on terminated microstrip feedline towards resonator is given by

or

Q can be determined by simple measurement of reflection coefficient

Example (dielectric resonator osc.)

Design 2.4GHz dielectric resonator oscillator using series feedback with bipolar transistor having S-parameters (Zo=50ohm); S11= 1.8 / 130o , S12= 0.4 / 45o , S21= 3.8 /36o, S22= 0.7 / -63o. Determine the required coupling coefficient for dielectric resonator and matching.

Solution

Circuit layout

continue

Calculate the Gout and Gin = GL using this formula

We obtain Gout = 10.7/132o. This corresponding to

Then

Network at resonator

Resonator should be placed at zero or 180o of phase from the transistor. So we have either 0.181 l (zero phase) or 0.431 l (180o phase)

d2= 0.181 l

Or = 0.431 l

Noise in oscillator

- Amplitude noise
- Phase noise
- Flicker noise

Phase noise-may be due to variation of device capacitance with variation of voltage.This is usually happened in amplifier.Amplitude noise may be converted to phase noise if the amplifier is present. Noises cause frequency instability in oscillator.

NCR (cont)

At oscillation

Where fo=oscillation frequency

And the gain condition (Barkhausen) for oscillation is gmRp=1

Thus, any changes will result

#%

NCR (cont)

In the oscillator model, the noise source is Rp .The noise current produced is

where

k=Boltzman const , T = absolute temp.

B= bandwidth

Since gm= 1/Rp and Iout= gm* Vin , the noise current can be transferred to input and hence Vin can be written as

**%%

NCR (cont)

Thus the Vout, can be obtained by substituting and squaring #% and **%% . We have

Taking B= 1 Hz and carrier voltage ,Vcarrier-rms

And the carrier power is given by

The noise to carrier ratio for SSB in Hz is given by

Where fm =offset frequency from carrier

NCR (cont)

For phase noise

Note: This ratio is half of the total noise since half will be converted to AM noise and half left for phase noise.

Example

Calculate the phase noise to carrier ratio of an oscillator of 10MHz with Q=100. Assume the inductor is 2 mH and the peak voltage across it is 10V. Let the noise figure is 10dB.

Flicker noise ( 1/f noise)

As in previous example

fm NCR

50kHz 170dB/Hz

30kHz 168.5dB/Hz

10kHz 159dB/Hz

Design for low 1/f noise

- Design procedures:-
- Choose high Q-factor of the resonator
- Choose low 1/f noise active components (e.g Bipolar transistor)
- Choose transistor with the lowest possibility of fT . For good rule of thumb fT< 2 x fosz .
- Low current best 1/f performance. Note that fT drops with low current.

(FET)

(HBT)

(BJT)

Maximum oscillation frequency

- For high Q-factor choose parts that have low losses:
- Resonator
- Series resistance of capacitors
- Series resistance of tuning diode
- PCB.

Measure phase noise from VNA (for checking)

- Verify power input signal no higher than 10dBm
- Reduce input attenuation to minimum (0 dB)
- Determine the carrier power at large video and resolution bandwidth at appropriate span (3MHz RBW, 1MHz VBW,50MHz span.
- Set span for single sideband ( desired offset frequency)
- Reduce VBW to 10 Hz, RBW to 1 kHz.
- Set marker to the carrier. Select marker to show the frequency offset.
- Move the marker along the SSB phase noise curve and take reading. MAX HOLD for maximum phase noise power( let the spectrum settle for 5 minutes )
- Note that cable insertion loss should also be determined

Reducing Phase Noise in Oscillators

1. Maximize the Qu of the resonator.

2. Maximize reactive energy by means of a high RF voltage across the resonator. Use a low LC ratio.

3. Avoid device saturation and try to use anti parallel (back to back) tuning diodes.

4. Choose your active device with the lowest NF (noise figure).

5. Choose a device with low flicker noise, this can be reduced by RF feedback. A bipolar transistor with an unby-passed emitter resistor of 10 to 30 ohms can improve flicker noise by as much as 40 dB. - see emitter degeneration

6. The output circuits should

YIG equivalent circuit

fo=resonance frequency=nHo

where

V= volume of YIG sphere

k=1/d1=coupling factor and d1 is the loop diameter

wm= 2pfm=2pn (4p Ms)

Ho= dc magnetic filed

n= gyro magnetic ratio ( 28 GHz/Tesla)

DH= resonance line width

L1= self inductance of the loop

4pMs= saturation magnetism

Effects of ambient changes on stability in oscillators

A frequency change of a few tens of hertz back and forth over a couple of minutes would mean nothing to an entertainment receiver designed for the FM Radio band. Such a drift in an otherwise contest grade receiver designed to receive CW (morse code) would be intolerable. It's a question of relativity.

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