
EEGN-CSCI 660 Introduction to VLSI Design Lecture 5. Khurram Kazi. Overview of Synthesis flow. Fundamental Steps to a Good design. If you have a good start, the project will go smoothly Partitioning the Design is a good start Partition by: Functionality
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+
B
Mux
sum
C
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D
select
Resource SharingHDL Description
if (select) then
sum <= A + B;
Else
sum <= C + D;
A
mux
C
select
+
sum
B
mux
D
Another Implementation: shared resource Implementation -> Area-efficient
One Possible Implementation
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* + -
>= < <=
= /= ==
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fastest
Carry Look Ahead
+
smallest
Ripple Carry
Synthetic Module
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A
B
C
D
E
SUM1 <= A + B + C;
SUM2 <= A + B + D;
SUM3 <= A + B + E;
+
+
+
+
SUM1
SUM2
SUM3
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sum1 <= A + B + C;
sum2 <= B + A + D; -> not sharable
sum3 <= A + B + E; -> sharable
sum1 <= A + B + C;
sum2 <= D+ A + B; -> not sharable
sum3 <= E +(A + B); -> sharable
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A
B
Cin
+
sum
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A
+
B
+
C
+
Z
D
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A
+
B
+
Z
C
+
D
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C
+
B
+
D
+
Z
A
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The path between reg1 and reg2 is divided between three different block
Due to hierarchical boundaries, optimization of the combinatorial logic cannot be achieved
Synthesis tools (Synopsys) maintain the integrity of the I/O ports, combinatorial optimization cannot be achieved between blocks (unless “grouping” is used).
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All the combinatorial circuitry is grouped in the same block that has its output connected the destination flip flop
It allows the optimal minimization of the combinatorial logic during synthesis
Allows simplified description of the timing interface
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Simplifies the synthesis design environment: Inputs to the individual block arrive within the same relative delay (caused by wire delays)
Don’t really need to specify output requirements since paths starts at flip flop outputs.
Take care of fanouts, rule of thumb, keep the fanout to 16 (dependent on technology and components that are being driven by the output)
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Due to time pressures, and a bug found that can be simply be fixed by adding some simple glue logic. RESIST THE TEMPTATION!!!
At this level in the hierarchy, this implementation will not allow the glue logic to be absorbed within any lower level block.
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reg1 may be driven by time critical function, hence will have different optimization constraints
reg3 may be driven by slow logic, hence no need to constrain it for speed
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set_max_capacitance
Set_max_transition
& set_max_fanout
on Inputs and Output ports or current design
set_operating_conditions
on the whole design
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-min_version <min library filename>
dc_shell> set_min_library “ex25_worst.db” \
-min_version “ex25_best.db”
This command allows the users to simultaneously specify the best case and worst case libraries. Can be used to fix set up and hold violation. The user should set both the min and the max values for the operating conditions
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dc_shell> set_operating_conditions WORST
dc_shell> set_operating_conditions –min BEST
-max WORST
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“20 x 20”
“10 x 10”
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set_wire_load_model –name <wire-load model>
dc_shell>set_wire_load_model –name MEDIUM
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set_wire_load_mode <top|enclosed|segmented>
dc_shell>set_wire_load_mode top
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50x50
40x40
40x40
30x30
30x30
20x20
20x20
50x50
40x40
Wire load models across hierarchymode = top: (ignores lower level wire loads)
mode = enclosed: (uses best fitting wire loads)
mode = segmented: (uses several wire loads)
50x50
40x40
30x30
20x20
40x40
20x20
30x30
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set_drive <value><object list>
dc_shell> set_drive 0 {clk rst}
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set_driving_cell –cell <cell name> -pin <pin name> <object list>
dc_shell>set_driving_cell –cell BUFF1 –pin Z [all_inputs]
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set load <value> <object list>
dc_shell>set_load 1.5 [all_outputs]
dc_shell> set_load 0.3 [get_nets blockA/n1234]
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set_max_transition <value> <object list>
set_max_capacitance <value> object list>
set_max_fanout ,value> <object list>
dc_shell –t>set_max_transition 0.3 current_design
dc_shell –t>set_max_capacitance 1.5 [get_ports out1]
dc_shell –t>set_max_fanout 3.0 [all_outputs]
(dc_shell –t> corresponds to DC operating in tcl mode)
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dc_shell –t >create_clock –period 40
-waveform [list 0 20] CLK
set_dont_touch_network is a very useful command and is usually used for clock and reset. It is used to set_dont_touch property on a port, or a net. This prevents DC from buffering the net in order to meet DRCs.
dc_shell –t>set_dont_touch_network {clk, rst}
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dc_shell –t>set_dont_touch current_design
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