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Verification of Clock Domain Refinements in the Synchronous Design Environment

Verification of Clock Domain Refinements in the Synchronous Design Environment. Tarvo Raudvere Royal Institute of Technology tarvo@imit.kht.se. Outline. ForSyDe Introduction Verification problems in refinement: Local – polynomial abstraction Global – value preserving refinement

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Verification of Clock Domain Refinements in the Synchronous Design Environment

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  1. Verification of Clock Domain Refinements in the Synchronous Design Environment Tarvo Raudvere Royal Institute of Technology tarvo@imit.kht.se

  2. Outline • ForSyDe Introduction • Verification problems in refinement: • Local – polynomial abstraction • Global – value preserving refinement • Example – refinement and verification of the Audio Equalizer • Conclusion

  3. ForSyDe (Formal System Design) • Objective • Addresses the design of reactive system-on-chip applications with control and data flow parts • Foundations • Start with a purely functional and deterministic system specification • Uses a synchronous model of computation • Uses a functional modeling language with formal semantics • Allows for formally defined design transformation • Allows to interpret the system model into a hardware and software interpretation

  4. Specification Model DesignConstraints Functional Domain Design Refinement Verification Transf. Library Implement. Model Implementation Mapping Implementation Domain HW Description Interface Description SW Description The ForSyDe Design Flow

  5. Specification Model • Is based on a synchronous model of computation • Is purely functional and deterministic • Uses process constructors • Uses possibly infinite/ideal data types • Implies a concurrent process model • Can be refined during design transformations

  6. Tag Process 3 2 1 0 1 8 2 Value Event AbsentValue Synchronous Assumptions –Absent and Present events Timing Signal 3 2 1 0 2 9 3 Computation

  7. Semantic PreservingTransformation Do not change the meaning of the model Used mainly for process merging and splitting M1 Mn ImplementationModel T1 T2 Tn The specification model (M0) is stepwise refined by the use of well defined design transformation (Ti) into an implementation model (Mn) Refinement of the Specification Model Specification Model M0 • Design DecisionTransformation • Change the meaning of the model • Introduce a design decision • Examples are refinement of data types, constraining buffer sizes

  8. s2 s1 Data path Reg. file P5 delay Δ(0) s5 FSM P4 (+1) s6 s4 s1 s3 P1 (+1) P2 (+) P3 (+1) s2 A Clock Domain Refinement

  9. Consequences • More clock cycles for the computation • Clock domain, which works on a higher speed • Local property : Is the computation result the same as in the combinational process • There is one clock cycle computation delay • Global property : which kind of influences the delay causes to the rest of the system

  10. Global property – Value preserving clock domain refinement Local property – polynomial abstraction Solutions P5 delay Δ(0) s5 P4 (+1) s6 s4 s3 Δ (┴) P2 (+) P3 (+1) Data R s1 s2 FSM

  11. Polynomial Abstraction • Verification of sequentially implemented combinational functions • Applicable at a high abstraction level • Target: clock domain refinements in the ForSyDe methodology

  12. x f y f(x,y,z) x z DATA PATH f(x,y,z) y z + × x + + + CONTROLLER y f(x,y,z) × × × z Clock Domain Refinement

  13. D D D d1 d2 d3 d4 c1 c2 c3 c4 × × × × + + + Refinement of a FIR-filter Combinational Specification f=c1d1+…+c4d4 ( g ≡ f ) ??? d1 0 reg g × + mux mux d4 c1 Sequential Implementation mux c4 ready FSM start

  14. Theoretical background • ”The Fundamental Theorem of Algebra”: Two degree k uni-variable polynomials are equivalent, if they evaluate pairwise the same values for k+1 input assignments. • Example • S(x)=4x2+3x+7 • R(x)= 5x2+2x+6 • Degree of S(x) and R(x) is 2 • S(x)=R(x), if they calculate pairwise the same value for 3 arbitrary chosen input assignments • If S(x)=R(x) for 3 input assignments, then they are equal for any input assignment.

  15. D D D d1 d2 d3 d4 c1 c2 c3 c4 × × × × f + + + d1 g 0 reg d4 × + mux mux c1 c4 mux ready FSM start Strategy • Find degrees of c1, c2, c3, c4, d1, d2, d3, d4 in f and g. • According to the degrees declare domains of input values. • The equivalence check of f and g can be performed by a model checker. • It is possible to reduce domains of these input signals, which do not determine the control flow of the FSM.

  16. Methodology Sequential design Signal type? • Signal type classification • Degree calculation • Abstraction, model checking Symbolic execution Data 1. 2. Control Output polynomials 3. Degree calculation Domain declaration Model checking Abstract model

  17. Model Checking • Control inputs may get values from all the range of their input domains. • The data signal s gets assignments from 0 to n, if the degree of s is n. • Specification - S(x), Implementation - I(x) the model checker verifies the property: “always S(x)=I(x), if the signal ready is high”.

  18. Refinement of the Equalizer System Model Button Control Dist. Control HoldLevel LevelControl Distort.Control CheckLow Freq Buttons PowerSpectrum FIR1 Amplifier Audio Filter FFT AudioIn FIR2 Amplifier Sum GroupSamples FIR5 Amplifier Audio Analyzer AudioOut

  19. 5 order-4 FIR-filters 29 Integer inputs 210 seconds 13M BDD-nodes Case Study: Verification of the Audio Filter Button Control Audio Filter FIR-filter1 Lowest Pass Amplifier FIR-filter2 Lowest Pass Amplifier + FIR-filter5 Lowest Pass Amplifier

  20. Value preserving clock domain refinement – dataflow model 2 5 Δ (0) 5 2 0 3 2 1 +1 + 4 3 2 9 5 2

  21. After a block refinement (a) Δ (0) 0 conflict 3 2 1 +1 Δ (┴) + ┴

  22. After a block refinement (b) – synchronous model ┴,2,┴,5,┴ 0,┴,2,┴,5,┴ Δ (0) Δ (┴) Pattern: (v, ┴) 5,┴,2,┴,0,┴ 9,┴,5,┴,2,┴ ┴ 3 ┴ 2 ┴ 1 +1 Δ (┴) 4,┴,3,┴,2,┴ + Pattern: (v, ┴) Pattern: (┴,v)

  23. Advantage: Dataflow and synchronous models have the same functionality Disadvantages It is possible to execute only one process at time in a loop which contains n computation blocks. The system must run n+1 times faster Value preserving refinement

  24. +1 + +1 +1 Δ (┴) + +1 Δ (┴) +1 R + +1 R Possible design flow Synchronous data flow model Synchronous multirate model Hardware model VHDL

  25. Refinement of the Equalizer System Model Button Control Dist. Control HoldLevel LevelControl Distort.Control CheckLow Freq Buttons PowerSpectrum Audio Filter FIR1 FIR1 Amplifier Amplifier FFT FFT AudioIn FIR2 FIR2 Amplifier Amplifier Sum Sum GroupSamples FIR5 FIR5 Amplifier Amplifier Audio Analyzer AudioOut

  26. Conclusion • In the ForSyDe methodology designs are refined through design transformations • Verification of clock domain refinements • Polynomial abstraction • Value preserving refinement of clock domains • http://www.imit.kth.se/info/ForSyDe

  27. Thanks for your attention!

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