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Bit Error Rate Transceiver

Bit Error Rate Transceiver. Jordan C. Grosh and Samuel E. Moelius III {jkgrosh,moelius}@udel.edu (617 LUTs). Linear Feedback Shift Register Interface. * reg is an internal std_logic_vector(7 downto 0). Linear Feedback Shift Register (cont.). On rising edge of clkin:

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Bit Error Rate Transceiver

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  1. Bit Error Rate Transceiver Jordan C. Grosh and Samuel E. Moelius III {jkgrosh,moelius}@udel.edu (617 LUTs)

  2. Linear Feedback Shift Register Interface * reg is an internal std_logic_vector(7 downto 0).

  3. Linear Feedback Shift Register (cont.) • On rising edge of clkin: reg(7) <= reg(1) xor reg(2) xor reg(3) xor reg(7); reg(6) <= reg(0) xor reg(1) xor reg(2) xor reg(6); reg(5) <= reg(0) xor reg(2) xor reg(3) xor reg(5) xor reg(7); reg(4) <= reg(3) xor reg(4) xor reg(6) xor reg(7); reg(3) <= reg(2) xor reg(3) xor reg(5) xor reg(6); reg(2) <= reg(1) xor reg(2) xor reg(4) xor reg(5); reg(1) <= reg(0) xor reg(1) xor reg(3) xor reg(4); reg(0) <= reg(0) xor reg(1) xor reg(7); • This is the result of iterating reg(7) <= reg(6) <= reg(5) <= reg(4) <= reg(3) <= reg(2) <= reg(1) <= reg(0) <= reg(1) xor reg(2) xor reg(3) xor reg(7); eight times.

  4. BERT Interface

  5. BERT Transmitter a <= "010"; dbusin <= 1024 + ext_divlsb; set clock divisor write <= ‘0’; write <= ‘1’; a <= "000"; dbusin <= lfsr.dbusout;* a <= “111”;** write <= ‘0’; write <= ‘1’; Yes dbusout(2) = ‘1’? null; a <= “001”;** No * lfsr.clkin is tied to int. ** read is held low throughout.

  6. BERT Receiver: Synchronization set clock divisor---same as in transmitter count <= (1024 + ext_divlsb)  8 - 1;* * count is an internal integer. 0 1 din Yes count = ‘0’? count = ‘0’? No No Yes ** read is held low throughout. *** lfsr.dbusin is “00000001” throughout. count <= count - 1; a <= "001";** lfsr.write <= ‘0’;*** ready <= ‘0’; lfsr.write <= ‘1’;

  7. BERT Receiver: Main Loop Yes dbusout(3) = ‘1’? null; a <= “100”; No a <= “001”; dbusout /= lfsr.dbusout?* No No a <= “111”; null; Yes No error /= 15? Yes error <= error + 1; * lfsr.clkin is tied to int.

  8. Achievements • Critical path is 7.95 ns • Peak (theoretical) operating frequency  125 MHz • Latches are not always bad! • A simple synchronization method • Additional Features • Ready signal • Adjustable clock divisor

  9. Tool Flow Design / Coding • Logical design. • Initial coding. • Revision and bug-fixes. Pre-synthesis Simulation • Testbench addresses: • Receiver and transmitter synchronize. • Error-count remains stable at zero when no errors are introduced. • Error-count increases when errors are introduced. Synthesis • Ensure that code is synthesizable. Post-synthesis Simulation • Ensure that synthesized code has same behavior under pre-synthesis testbench as pre-synthesis code. On-board Testing • Testing includes: • Receiver and transmitter synchronize when on separate boards. • Error-count remains stable at zero initially after synchronization. • Error-count saturates when connection is broken and then restored.

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