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Acceleration. How to improve speed? At what costs?. T=Nq * CPI * Cycletime. Nq, Number of instructions CPI, Cycles Per Instruction Cycletime. Single Cycle Design. CPI = 1 Cycletime = Long (Longest path). Multiple Cycle. 1 < CPI < S Cycletime = Factor 1/S. Pipelined design.

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Presentation Transcript
acceleration
Acceleration
  • How to improve speed?
  • At what costs?
t nq cpi cycletime
T=Nq * CPI * Cycletime
  • Nq, Number of instructions
  • CPI, Cycles Per Instruction
  • Cycletime
single cycle design
Single Cycle Design
  • CPI = 1
  • Cycletime = Long (Longest path)
multiple cycle
Multiple Cycle
  • 1 < CPI < S
  • Cycletime = Factor 1/S
pipelined design
Pipelined design
  • CPI = 1, (Constant)
  • Cycletime = Factor 1/S
throughput
“THROUGHPUT”
  • The total amount of work done in a given time
slide7
INSTRUCTION MEMORY STAGE (IM)

Zeroext.

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logic

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ALU

4

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INSTRUCTION

MEMORY

slide8
INSTRUCTION DECODE STAGE (DE)

Zeroext.

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logic

0

A

ALU

4

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slide9
INSTRUCTION EXECUTE STAGE (EX)

Zeroext.

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logic

0

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4

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slide10
DATA MEMORY STAGE (DM)

Zeroext.

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logic

0

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DATA MEMORY

slide11
WRITEBACK STAGE (WB)

Zeroext.

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logic

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pipeline
Pipeline
  • 5 stages, (IM, DE, EX, DM, WB)
  • Writeback NOT in critical path
  • Cut critical path by 4
slide13
WRITEBACK STAGE (WB)

Zeroext.

CAN READ/WRITE

THE SAME REG!

Branch

logic

0

A

ALU

4

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+

31

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single cycle
Single Cycle

Reg

IM

DM

Reg

Reg

IM

DM

Reg

single cycle1
Single Cycle

Reg

IM

DM

Reg

Reg

IM

DM

Reg

4 stage pipe
4 Stage Pipe

Reg

IM

DM

Reg

Reg

IM

DM

Reg

Reg

IM

DM

Reg

Reg

IM

DM

Reg

a program
A Program

0x30 sub $6 $0 $1

0x34 add $7 $0 $1

0x38 ori $2 $0 0xABCD

0x3C sw $5 4($0)

$1 holds value 0x05

4 stage pipe1
4 Stage Pipe

Reg

  • 0x30 sub $6 $0 $1

IM

DM

Reg

  • 0x34 add $7 $0 $1

Reg

IM

DM

Reg

  • 0x38 ori $2 $0 0xABCD

Reg

IM

DM

Reg

  • 0x3C sw $5 4($0)

Reg

IM

DM

Reg

step 1
Step 1

Reg

  • 0x30 sub $6 $0 $1

IM

DM

Reg

  • 0x34 add $7 $0 $1

Reg

IM

DM

Reg

  • 0x38 ori $2 $0 0xABCD

Reg

IM

DM

Reg

  • 0x3C sw $5 4($0)

Reg

IM

DM

Reg

step 2
Step 2

Reg

  • 0x30 sub $6 $0 $1

IM

DM

Reg

  • 0x34 add $7 $0 $1

Reg

IM

DM

Reg

  • 0x38 ori $2 $0 0xABCD

Reg

IM

DM

Reg

  • 0x3C sw $5 4($0)

Reg

IM

DM

Reg

step 3
Step 3

Reg

  • 0x30 sub $6 $0 $1

IM

DM

Reg

  • 0x34 add $7 $0 $1

Reg

IM

DM

Reg

  • 0x38 ori $2 $0 0xABCD

Reg

IM

DM

Reg

  • 0x3C sw $5 4($0)

Reg

IM

DM

Reg

step 4
Step 4

Reg

  • 0x30 sub $6 $0 $1

IM

DM

Reg

  • 0x34 add $7 $0 $1

Reg

IM

DM

Reg

  • 0x38 ori $2 $0 0xABCD

Reg

IM

DM

Reg

  • 0x3C sw $5 4($0)

Reg

IM

DM

Reg

step 5
Step 5

Reg

  • 0x30 sub $6 $0 $1

IM

DM

Reg

  • 0x34 add $7 $0 $1

Reg

IM

DM

Reg

  • 0x38 ori $2 $0 0xABCD

Reg

IM

DM

Reg

  • 0x3C sw $5 4($0)

Reg

IM

DM

Reg

slide24
Zeroext.

Branch

logic

0

A

ALU

4

B

+

31

+

Sgn/Ze

extend

  • > 0x30 sub $6 $0 $1
  • 0x34 add $7 $0 $1
  • 0x38 ori $2 $0 0xABCD
  • 0x3C sw $5 4($0)
slide25
Zeroext.

Branch

logic

0

A

ALU

4

B

+

31

+

Sgn/Ze

extend

  • 0x30 sub $6 $0 $1
  • > 0x34 add $7 $0 $1
  • 0x38 ori $2 $0 0xABCD
  • 0x3C sw $5 4($0)
slide26
Zeroext.

Branch

logic

0

A

ALU

4

B

+

31

+

Sgn/Ze

extend

  • 0x30 sub $6 $0 $1
  • 0x34 add $7 $0 $1
  • > 0x38 ori $2 $0 0xABCD
  • 0x3C sw $5 4($0)
slide27
Zeroext.

Branch

logic

0

A

ALU

4

B

+

31

+

Sgn/Ze

extend

  • 0x30 sub $6 $0 $1
  • 0x34 add $7 $0 $1
  • 0x38 ori $2 $0 0xABCD
  • > 0x3C sw $5 4($0)
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