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Exploring VHDL Programming for FPGA: DIO2 Peripheral and FC16 Control

This lecture covers the integration of VHDL with the Digilab D2E Development Board and the DIO2 Peripheral Board using the FC16 Forth Core. Key topics include accessing the DIO2 peripheral, implementing control processes in VHDL, and executing opcodes for LED displays and button handlers. The lecture also discusses buffer architectures, multi-cycle control, and effective data handling techniques, providing a practical understanding of FPGA programming and peripheral interfacing.

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Exploring VHDL Programming for FPGA: DIO2 Peripheral and FC16 Control

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  1. Programming Example Lecture 8.6 A VHDL Forth Core for FPGAs: Sect. 7

  2. Digilab D2E Development Board

  3. Digilab D2E Development Board

  4. Digilab DIO2 Peripheral Board

  5. Digilab DIO2 Peripheral Board

  6. Using the FC16 Forth Core DIO2@ ( addr – data ) DIO2! ( data addr -- )

  7. Accessing the DIO2 Peripheral Board DIO2@ ( addr – data ) DIO2! ( data addr -- )

  8. buff3.vhd en library IEEE; use IEEE.STD_LOGIC_1164.all; entity buff3 is generic (width:positive); port( input : in STD_LOGIC_vector(width-1 downto 0); en : in STD_LOGIC; output : out STD_LOGIC_vector(width-1 downto 0) ); end buff3; architecture buff3 of buff3 is begin output <= input when en = '1' else (others => 'Z'); end buff3; input output

  9. Seven-segment LED display

  10. In opcodes.vhd constant DIO2store: opcode := X"010F"; -- DIO2! constant LCDistore: opcode := X"0110"; -- LCDinst! constant LCDdstore: opcode := X"0111"; -- LCDdata!

  11. In FC16_control add…. signal ccycle: STD_LOGIC_VECTOR (5 downto 0); MultiCC: process (clk, clr, current_state) begin if clr = '1' then ccycle <= "000001"; elsif (clk'event and clk = '1') then if current_state = exec then ccycle <= ccycle + 1; else ccycle <= "000001"; end if; end if; end process MultiCC;

  12. In FC16_control add…. when exec => -- execute instr without fetching next one if (icode = X"010E" or icode = X"010F") and ccycle < 3 then next_state <= exec; elsif (icode = X"0110" or icode = X"0111") and ccycle < 8 then next_state <= exec; --elsif icode = X"Code_for_multi-cycle" -- and ccycle < Num_cc_to_exec then -- next_state <= exec; else next_state <= fetch; -- go to fetch state end if;

  13. In FC16_control add…. DIO2! ( data addr .. ) when DIO2store => cs <= '1'; oe <= '0'; pinc <= '0'; if ccycle = 1 then we <= '1'; else tload <= '1'; nload <= '1'; tsel <= "111"; nsel <= "01"; dpop <= '1'; end if;

  14. From DIO2 CPLD data_out <= btns(7 downto 0) when addr(1 downto 0) = "00" else '0'& btns(14 downto 8) when addr(1 downto 0) = "01" else switchs; In opcodes.vhd constant DIO2fetch: opcode := X"003A"; -- DIO2@ In FC16_control.vhd when DIO2fetch => -- read 8-bit DIO2-bus (E1) tload <= '1'; -- DIO2@ ( addr – data ) tsel <= "100"; cs <= '1'; oe <= '1'; In FC16.vhd E1 <= ground & data_io; data <= data_io;

  15. \ Test of DIO2 buttons, LEDs, and 7-seg displays : D2DIG! ( n -- ) \ Display n on 7-segment displays DUP 8 RSHIFT \ n nHI 7 DIO2! \ display nHI 6 DIO2! ; \ display nLO : D2LD! ( n -- ) \ Display n on the 16 LEDs DUP 8 RSHIFT \ n nHI 5 DIO2! \ display nHI 4 DIO2! ; \ display nLO : get.BTN2 ( -- n ) \ Push 15-button bit mask to T 1 DIO2@ \ btns(15:8) 8 LSHIFT 0 DIO2@ \ btns(7:0) OR ;

  16. : waitBTN2 ( -- n) \ Wait to push a button and get mask BEGIN \ wait to lift finger get.BTN2 0= UNTIL BEGIN \ wait to press button get.BTN2 UNTIL get.BTN2 ; \ get buttons

  17. : but>num ( n1 -- n2 ) \ convert button bit mask to button no. 15 FOR \ loop 15 times DUP 1 = IF \ value matches R> \ get loop value 15 SWAP - \ find index 1 >R \ break out of loop ELSE U2/ \ Shift button value THEN NEXT NIP ; \ remove extra 1 from N

  18. : main ( -- ) \ main program BEGIN waitBTN2 \ wait to push BTN2 DUP D2LD! \ display on LEDs but>num \ find button number D2DIG! \ display on 7-seg display AGAIN ;

  19. type rom_array is array (NATURAL range <>) of STD_LOGIC_VECTOR (15 downto 0); constant rom: rom_array := ( JMP, --0 X"0047", --1 -- D2DIG! dup, --2 LIT, --3 X"0008", --4 rshift, --5 LIT, --6 X"0007", --7 DIO2store, --8 LIT, --9 X"0006", --a DIO2store, --b RET, --c -- D2LD! dup, --d LIT, --e X"0008", --f rshift, --10 LIT, --11 X"0005", --12 DIO2store, --13 LIT, --14 X"0004", --15 DIO2store, --16 RET, --17

  20. -- get.BTN2 LIT, --18 X"0001", --19 DIO2fetch, --1a LIT, --1b X"0008", --1c lshift, --1d LIT, --1e X"0000", --1f DIO2fetch, --20 orr, --21 RET, --22 -- waitBTN2 CALL, --23 X"0018", --24 zeroequal, --25 JZ, --26 X"0023", --27 CALL, --28 X"0018", --29 JZ, --2a X"0028", --2b CALL, --2c X"0018", --2d RET, --2e

  21. -- btn>num LIT, --2f X"000f", --30 tor, --31 dup, --32 LIT, --33 X"0001", --34 eq, --35 JZ, --36 X"0042", --37 rfrom, --38 LIT, --39 X"000f", --3a swap, --3b minus, --3c LIT, --3d X"0001", --3e tor, --3f JMP, --40 X"0043", --41 u2slash, --42 drjne, --43 X"0032", --44 nip, --45 RET, --46

  22. -- main CALL, --47 X"0023", --48 dup, --49 CALL, --4a X"000d", --4b CALL, --4c X"002f", --4d CALL, --4e X"0002", --4f JMP, --50 X"0047", --51 X"0000" --52 );

  23. Relative speed of FPGA Forth core

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