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New xTCA Developments at SLAC. CERN xTCA for Physics Interest Grou p Sept 26, 2011 Ray Larsen SLAC National Accelerator Laboratory. Topics. Standards developments Applications Demonstration Program Future Plans. Standards. Hardware, Software working groups meet weekly/ needed

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new xtca developments at slac

New xTCA Developments at SLAC

CERN xTCA for Physics Interest Group

Sept 26, 2011

Ray Larsen

SLAC National Accelerator Laboratory

New xTCA Developments at SLAC - R. Larsen

topics
Topics

Standards developments

Applications Demonstration Program

Future Plans

New xTCA Developments at SLAC - R. Larsen

standards
Standards
  • Hardware, Software working groups meet weekly/ needed
  • 2 new HW standards approved
    • ATCA
      • PICMG3.8 Standard IO interface to Rear Transition Module (RTM), IPMI extension & power connector
    • MTCA
      • MTCA.4 Crate, 2-wide AMC & RTM, IO interface, IPMI extension and power pins designated

New xTCA Developments at SLAC - R. Larsen

standard extensions for physics
Standard Extensions for Physics

New xTCA Developments at SLAC - R. Larsen

standards details
Standards Details
  • ATCA PICMG3.8
    • 120 5GHz BW IO channels on 3- 4x10 ZD connectors
    • New connector (Positronix) for IPM, power
    • Mechanical, E-keying functions
    • Implemented on SLAC MPP Processor (M. Huffer)
  • MTCA.4
    • Extends double-wide shelf (crate) to include RTM
    • 60 ChIO, IPMI on 2- 3x10 ZD connectors
    • Extended backplane timing, trigger, interlocks layer
    • Compatible with all existing 1-wide AMC products
    • Implemented by Schroff, ELMA, PT, others in dev’mt

New xTCA Developments at SLAC - R. Larsen

slide6

PICMG3.8 RTM Interface Standard

Rear View

120 - IO Channels (3x40)

IPMI, Power Connector (blue)

2 Mechanical Keys

Courtesy M. Huffer, SLAC

New xTCA Developments at SLAC - R. Larsen

mtca 4 amc rtm shelf concept
MTCA.4 AMC-RTM-Shelf Concept

New xTCA Developments at SLAC - R. Larsen

mtca 4 12 amc backplane
MTCA.4 12-AMC Backplane

Intlk, Vector Sums

Parallel Triggers

New xTCA Developments at SLAC - R. Larsen

slide9

MTCA.4 Backplane Timing Distribution

2 radial clocks per AMC,low jitter

MCH

Cross-

Point-Switch

Backplane

Central Timing

AMC

Timing

AMC

ADC

AMC

ADC

Enc.Clock

Enc.Clock

Trigger

Trigger

Interlock

Interlock

8 bussed lines,M-LVDS for

Clocks, triggers, interlocks

Courtesy K. Rehlich, DESY

New xTCA Developments at SLAC - R. Larsen

rtm extended ipmi circuit
µRTM Extended IPMI Circuit

New xTCA Developments at SLAC - R. Larsen

mtca 4 prototype shelves modules
MTCA.4 Prototype Shelves & Modules

Emerging New Electronics Standards - R. Larsen

mtca 4 12 slot shelf dual star
MTCA.4 - 12 Slot Shelf Dual Star

Back-Plane

Dual PU slot

Dual MCH Slot

12 Payload AMC-RTMs Dual Star Redundant Front View

New xTCA Developments at SLAC - R. Larsen

mtca 4 6 slot shelf non redundant
MTCA.4 - 6-Slot Shelf Non-Redundant

6 Slot Development Shelf

1-Star Non- Redundant

Front View

6-Slot Rear View

Courtesy Schroff, Struck

New xTCA Developments at SLAC - R. Larsen

slac applications demonstrations
SLAC Applications Demonstrations

LLRF for Main Linac S-Band 50MW station

Klystron interlocks for 10MW L-Band station

Beam Position Monitors for LCLSII Injector

New xTCA Developments at SLAC - R. Larsen

1 s band llrf
1. S-Band LLRF
  • Demonstrate intra-pulse feedback to achieve ~30fs phase control
    • Lower noise RF front end chassis
    • New solid state sub-booster
    • Feedback loop implemented in MTCA.4 using Struck 10 Ch ADC 2 Ch DAC developed w/DESY
    • New LCLSI waveguide water-stabilized rack
    • Test on Standby triggering, switch to Accelerate
  • Tests on accelerator to complete Oct 2011

New xTCA Developments at SLAC - R. Larsen

llrf mtca rf chassis testing
LLRF MTCA & RF Chassis Testing

New xTCA Developments at SLAC - R. Larsen

rear view
Rear View

New xTCA Developments at SLAC - R. Larsen

rtm inputs
RTM Inputs

Note – Preliminary RTM shown

Final RTM

with full IPMI complete, In test.

New xTCA Developments at SLAC - R. Larsen

rf chassis reference lo sources downmixers
RF Chassis – Reference, LO, Sources, Downmixers

Note – Next stage

plan is to test L-Band down-mixers, other RF modules in

MTCA card format

New xTCA Developments at SLAC - R. Larsen

amc 10 2ch adc dac 16bit 125 msps
AMC - 10/2Ch ADC/DAC 16bit 125 MSPS

Initial Applications:

LLRF DESY XFEL

LLRF SLAC Upgrade Proto

Photo courtesy M. Kirsch,

(Struck )

Emerging New Electronics Standards - R. Larsen

rtm 10 ch adc dac ipmi interface
RTM 10 Ch ADC-DAC, IPMI Interface
  • Rear Panel
  • Mini-Coax IF Signals In
  • RF Ref In
  • Trigger in
  • Dual I&Q DAC Out
  • IPMI Extension to RF Chassis

Courtesy A. Young, SLAC

Emerging New Electronics Standards - R. Larsen

2 mtca klystron interlocks s l band
2. MTCA Klystron Interlocks S&L Band
  • FPGA based interlocks in MTCA.4
    • S-Band interlocks currently in separate FPGA non-modular chassis
    • L-Band interlocks currently FPGA based in VME
    • MTCA solution will serve both in future
    • SLAC designed RTM mates to new TEWS Spartan 6 FPGA module (just received in US)
    • RTM testing starting
    • 1 board pair serves 8 Ch-60MSps, 16 Ch-2KSps
    • 2 board pairs serve 1 S- or L-band station

New xTCA Developments at SLAC - R. Larsen

rtm fpga interlocks
RTM FPGA Interlocks
  • Rear Panel
  • Inputs
  • - 8-60 MSps Ch
  • - 16-2 KSps Ch
  • - 12 bits Diff +/- 1V
  • - Diode protection
  • All channels
  • Outputs
  • - Interlock Sums
  • RF Interlocks for
  • L-Band 1 msec, S-band 1.5 µsec

Courtesy D.G. Brown, SLAC

Emerging New Electronics Standards - R. Larsen

amc tamc651 fpga w rtm
AMC TAMC651 FPGA w/RTM

Courtesy TEWS

Note – Completion date for ESB installation Dec. 2011.

New xTCA Developments at SLAC - R. Larsen

3 bpms for lcslii injector
3. BPMs for LCSLII Injector
  • Goal: Demonstration of 8 BPMs in 12-slot
    • RTM has 4 Ch analog plus calibration w/ strip-line coupling between 120 Hz pulses
    • AMCs will be 4 Ch 125 or 250 MSps (125 available now; 250 may be developed by commercial supplier(s)
    • 250 MSps needed if multibunch (2 bunches 8 nsec apart)
    • Requirements being finalized (16 bit ADCs)
    • Preliminary RTM layout indicates feasible

New xTCA Developments at SLAC - R. Larsen

bpm system block diagram
BPM System Block Diagram

Courtesy

S. Hoobler

et al, private communication

New xTCA Developments at SLAC - R. Larsen

conclusions 1
Conclusions 1
  • Standards for hardware have passed 2 major milestones
    • Committees will disband when SOWs complete
    • Software committee continues developing guidelines for architecture and protocols
    • Member labs remain involved in PICMG through Coordinating Committee for oversight, servicing tweaks
    • Start new initiatives, SOWs, form committees as needed

New xTCA Developments at SLAC - R. Larsen

conclusions 2
Conclusions 2
  • SLAC new initiatives open future opportunities
    • Main Linac RF upgrades for LCLSII, I.
    • BPM upgrades for LCLSII Injector, Main Linac
    • Interlock systems wholly contained in MTCA.4 combined RF-Controls package
    • Long range: Complete replacement CAMAC controls in 2-mile accelerator, $20M program
  • Timeline:
    • RF and interlock demos complete in Q1-2 FY12
    • BPM AIP completes Q2 FY13

New xTCA Developments at SLAC - R. Larsen