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A Scalable Programmable Baseband Platform for Energy-Efficient Reactive Software-Defined-Radio. B. Bougard (presenter), D. Novo, F. Naessens, L. Hollevoet, T. Schuster, M Glassee, A. Dejonghe, L. Van der Perre. CrownCom 2006 Mykonos, Greece June 9, 2006. Public hot-spot 802.11. Office

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A Scalable Programmable Baseband Platform for Energy-Efficient Reactive Software-Defined-Radio


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    1. A Scalable Programmable Baseband Platform for Energy-Efficient Reactive Software-Defined-Radio B. Bougard (presenter), D. Novo, F. Naessens, L. Hollevoet, T. Schuster, M Glassee, A. Dejonghe, L. Van der Perre CrownCom 2006 Mykonos, Greece June 9, 2006

    2. Public hot-spot 802.11 Office WLAN 802.11 ? Tomorrow’s new standard DVB-H DAB Fixed wireless access 802.16 Higher Rate Cellular Mobile A user’s dream:Anything, anywhere, anytime

    3. Today’s solution: multiple radios

    4. Software Defined Radio All cost factors direct us towards SDRs $ Time-to-Market $ Silicon Area $ #components $ Volume $ Various NRE

    5. SDR: a wireless dream come true? SDR

    6. Outline • Reactive SDR platform requirements • State-of-the-art • Design methodology for flexibility and low energy • Reactive radio platform architecture • Scalable platform interconnect • Reactive digital front-end • Coarse-Grain Array based baseband processor • Radio Control processor • Preliminary design results

    7. Outline • Reactive SDR platform requirements • State-of-the-art • Design methodology for flexibility and low energy • Reactive radio platform architecture • Scalable platform interconnect • Reactive digital front-end • Coarse-Grain Array based baseband processor • Radio Control processor • Preliminary design results

    8. Reactive Software defined radio: definition • Base-station SDR (90% SoA) • Terminal SDR -> hot topic - Single-mode Terminal SDR - Multi-mode Terminal SDR - Mode-configurable - Reactive radio - Cognitive radio Tier 4 – Ultimate Software Radio Tier 3 – Ideal Software Radio Tier 2 – SoftwareDefined Radio Tier 1 – Software Controlled Radio Tier 0 Hardware Radio

    9. Required Reactive radio platform features Low Cost Long HW lifespan Short SW deployment time Scalable HW/SW Energy scalable HW Energy scalable algorithms Energy scalable SW mapping Techno-aware energy managnt Versatile RX FE architecture Versatile TX FE architecture Powerful MAC/RLC/QoS Ctrl Energy Aware Spectrum Aware

    10. Outline • Reactive SDR platform requirements • State-of-the-art • Design methodology for flexibility and low energy • Reactive radio platform architecture • Scalable platform interconnect • Reactive digital front-end • Coarse-Grain Array based baseband processor • Radio Control processor • Preliminary design results

    11. SDR State-of-the-art: no global approach

    12. Mixed signal platform MPSOC Basebandprocessor SDR State-of-the-art: no global approach Scope Cognitiveradio Concurrency Management Reactive multi-mode Dynamic multi-thread Static multi-thread Single-modereconfigurable Single thread 1-10Mbps 10-100Mbps 5 ASM 100-1000Mbps 50 Processor C 500 Energy efficiency [Mips/mW] Performance Platform C Mapping productivity

    13. Mixed signal platform MPSOC Basebandprocessor SDR State-of-the-art: no global approach Scope Cognitiveradio Concurrency Management Reactive multi-mode Dynamic multi-thread Static multi-thread Single-modereconfigurable Single thread 1-10Mbps 10-100Mbps 5 ASM 100-1000Mbps 50 TI Processor C 500 Energy efficiency Performance Platform C Mapping productivity

    14. Mixed signal platform MPSOC Basebandprocessor SDR State-of-the-art: no global approach Scope Cognitiveradio Concurrency Management Reactive multi-mode Dynamic multi-thread Static multi-thread Single-modereconfigurable Single thread 1-10Mbps Sandbridge 10-100Mbps 5 ASM 100-1000Mbps 50 Processor C 500 Energy efficiency Performance Platform C Mapping productivity

    15. Mixed signal platform MPSOC Basebandprocessor SDR State-of-the-art: no global approach Scope Cognitiveradio Concurrency Management Reactive multi-mode Dynamic multi-thread Static multi-thread Single-modereconfigurable Single thread 1-10Mbps 10-100Mbps 5 ASM 100-1000Mbps 50 ICERA Processor C 500 Energy efficiency Performance Platform C Mapping productivity

    16. Mixed signal platform MPSOC Basebandprocessor SDR State-of-the-art: no global approach Scope Cognitiveradio Concurrency Management Reactive multi-mode Dynamic multi-thread Static multi-thread Single-modereconfigurable Single thread 1-10Mbps 10-100Mbps 5 ASM SH 100-1000Mbps 50 Processor C Energy efficiency Performance Platform C Mapping productivity

    17. Mixed signal platform MPSOC Basebandprocessor SDR State-of-the-art: no global approach Scope Cognitiveradio Concurrency Management Reactive multi-mode Dynamic multi-thread Static multi-thread Single-modereconfigurable Single thread 1-10Mbps 10-100Mbps 5 ASM EVP 100-1000Mbps 50 Processor C 500 Energy efficiency Performance Platform C Mapping productivity

    18. Mixed signal platform MPSOC Basebandprocessor SDR State-of-the-art: no global approach Scope Cognitiveradio Concurrency Management Reactive multi-mode Dynamic multi-thread Static multi-thread Single-modereconfigurable Single thread 1-10Mbps 10-100Mbps 5 ASM 100-1000Mbps 50 SODA Processor C 500 Energy efficiency Performance Platform C Mapping productivity

    19. Mixed signal platform MPSOC Basebandprocessor SDR State-of-the-art: no global approach Scope Cognitiveradio Concurrency Management Reactive multi-mode Dynamic multi-thread Static multi-thread Single-modereconfigurable Single thread 1-10Mbps 10-100Mbps 5 ASM 100-1000Mbps 50 Processor C 500 Energy efficiency Performance Platform C Mapping productivity

    20. Mixed signal platform MPSOC Basebandprocessor SDR State-of-the-art: no global approach Scope Cognitiveradio Concurrency Management Reactive multi-mode Dynamic multi-thread Static multi-thread Single-modereconfigurable Single thread 1-10Mbps 10-100Mbps 5 ASM 100-1000Mbps 50 Processor C 500 Energy efficiency Performance Objective Platform C Mapping productivity

    21. Energy scalable • front-end • baseband platform • air interface algorithm • protocols Joint quality-of-experienceand energy managementto translate energy scalability in low power operation Unique approach:Making flexibility rhyme with low-energy Holostic Approach for Low Energy

    22. Outline • Reactive SDR platform requirements • State-of-the-art • Design methodology for flexibility and low energy • Reactive radio platform architecture • Reactive digital front-end • Coarse-Grain Array based baseband processor • Radio Control processor • Preliminary design results

    23. Approach: Flexibility where needed • Ultra Low Power generic / low flexible listen/scan circuitry (Digital Front End) • Processor-based Digital Transceiver with aggressive power management • Processor power-overhead amortized by low utilization! Opportunistic partitioning • Typical Wireless LAN: Typical Cellular scenario: • Transmit 5% Transmit .5% • Receive 5% Receive .5% • Idle/Listen 90% Idle/Listen 99%

    24. Platform independent optimization Opportunisticpartitioning Platform architecturedefinition Inter-thread communication and RT management Interconnect refinement Threads implementation Cores Uarchitecturerefinement Virtual platform modeling SW mapping HW design Systematic methodology to design energy-aware SDR platform and software Application analysis and modeling

    25. DFE tile DFE tile DFE tile SyncPro SyncPro SyncPro Resulting platform template • ‘white box’ design environment: • true ESL flow • scalable retargetable virtual platform • Smooth HW/SW co-design, verification and test flow • SDR-tuned CGA: • C compiler • high performance- power ratio • ILP vs. DLP tradeoff Platform &MAC ctrl BW optimizedscalableinterconnect BB engine BB engine Scalability & Heterogeinity enabling flexibility @ low power through cross layer manager FEC engine L2 Periphand HI • Digital front end: • Solution for reactive radio • Ultra low power in standby

    26. Outline • Reactive SDR platform requirements • State-of-the-art • Design methodology for flexibility and low energy • Reactive radio platform architecture • Scalable platform interconnect • Reactive digital front-end • Coarse-Grain Array based baseband processor • Radio Control processor • Preliminary design results

    27. Scalable platform interconnect BB1 BB2 L2 mem

    28. ESL flow provides efficient debug/profiling/recycle environment Coware CSCTM

    29. Digital Front-end: Scalable autonomous detection/synchronization units • Multiple detection tiles allowing flexible support for MIMO reception and/or multi-mode scanning. • Tiles’ datapath is straight-through (no processor or controller is part of the data path). • Digital signal detection is performed in an application specific processor in each tile. • Hierarchical activation and configuration is performed by a global resource activity controller (RAC). • 5mW active power per (re)active tile (CMOS90)

    30. Hierarchical activation • Key idea: gradually enable the more power-consuming parts of the platform as the chance of a valid signal reception increases.

    31. Synchronization Processor Micro-architecture optimized for ultra-low-power CMOS 90 nm design 80MHz < 0.1 mW/MHz @ 0.7V including instruction fetch and load/store

    32. Select the right baseband processor CGA provides dense interconnection network matching DF CGA achieves very high IPC CGA provides low power through low instruction fetch freq. • Baseband processing is dataflow dominated • Baseband processing is computing intensive (4 op/memory access) • Wireless requires low power Low TTM requires programming ease • a tightly integrated combination of a VLIW DSP and a Coarse Grain Array • a dedicated ISA exploited DLP (intrinsic- controlled SIMD) • a compiler to map applications described in C directly on these architectures

    33. Fetch Instruction Dispatch Instruction Decode Central Registerfile FU FU FU … RC RC RC … RC RC RC … … RC RC RC Baseband architecture: ADRES 400MHz core 200-400MHz L1 25GOPS effective 64MOPS/mW 3 mm2 (with L1) Support IEEE 802.11n

    34. Outline • Reactive SDR platform requirements • State-of-the-art • Design methodology for flexibility and low energy • Reactive radio platform architecture • Reactive digital front-end • Coarse-Grain Array based baseband processor • Radio Control processor • Preliminary design results

    35. Preliminary design results

    36. Conclusions • CR spectrum data mining and agile air interface requirements claim for SDR implementations • To be viable, a SDR platform must be both low cost and low power • First step toward CR SDR platform: reactive radio platform • Heterogeneous MPSoC is best fit approach for SDR due to variety of task requirements. • Energy-scalable design coupled with adaptive joint QoS and energy management are the keys to bring flexibility and energy-efficiency together • We proposed a methodology to design energy-scalable SDR MPSoC architecture with balanced tradeoff between cost, energy efficiency and flexibility • We are designing such SoC targeting 802.11n, 802.16e and 3GPP-LTE standards (>100Mbps) • First results: • 90 nm CMOS • 2 Mgates • 2-10mW standby power (when reactive to at least one air interface) • <300mW average power when operating a standard

    37. Thank you!