Power- and Performance-Aware IP Mapping for NoC-Based MPSoC Platforms

1. Khalid Latif1, Amir-Mohammad Rahmani1, Tiberiu Seceleanu2, Hannu Tenhunen11University of Turku, Finland. 2ABB Corporate Research, Västerås, Sweden Power- and Performance-Aware IP Mapping for NoC-Based MPSoC Platforms

2. Networks-on-Chip (NoCs) Problem Allocation/Placement Prioritization Placement Algorithm Comparison with existing techniques Outline

3. An on-chip interconnection. Approach extracted from computer networks. Communication resources increase with the number of cores. Abstraction between computation and communication. Sophiticated routing algorithms. Plug and play platform. Solution for 100s of cores on a single chip. Networks-on-Chip router router router router ALU router router router router router router router router router router router router MPEG Profil MP3 Mem Mem DSP CoP Arb Ctrl Mng ACC FPU PE3 PE5 PE4 PE2 PE1 PE0 UP router router router router

4. All the benefits are provided at the cost of router area, power consumption, data packetization and de-packetization. Cache coherence is the big issue. Networks-on-Chip router router router router ALU router router router router router router router router router router router router MPEG Profil MP3 Mem Mem DSP CoP Arb Ctrl Mng ACC FPU PE3 PE5 PE4 PE2 PE1 PE0 UP router router router router

5. Typical NoC Networks-on-Chip router router router • Comprises: • Interconnects • Routers • Processing Elements router router router router router router router router router DSP Mem Mem Mng ACC CoP Arb Ctrl PE1 PE2 UP PE0

6. Typical NoC Key challenge: Flow control Store and forword Cut through Less buffer requirements Networks-on-Chip Time-Space diagrams 0 1 2 3 H B B B T H B B B T Channel H B B B T 0 1 2 3 H B B B T H B B B T Channel H B B B T 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Cycle 0 1 2 3 H B B B T H B B B T Channel H B B B T 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Cycle

7. Typical NoC Key challenge: Flow control Store and forword Cut through DEADLOCK!!! All channels are free. Networks-on-Chip IP1(HM) IP2 Interface Interface Interface IP3

8. Typical NoC Key challenge: Flow control Store and forword Cut through Overall higher throughput but problem for time critical applications. Good mapping/placement technique needed. Networks-on-Chip

9. Typical NoC Target: Minimization of communication cost. In terms of hop-count. Average hop-count should be one (Best case). Inturn, power optimization. Mapping Criteria: Cores communicating more often should be neighbors. Neighboring cores might not serve, when needed. High piriority core/process should be mapped to highly suitable position. Piriority? Suitable position? Networks-on-Chip

10. Core Piriority: Total number of packets to be communicated to-and-by the core. (Npi) Number of neighboring cores required. (Ni) Traffic distribution σxi2 (statistical varience): Number of neighbors of neighboring cores. (Nf) Core Prioritization

11. Placement Algorithm

12. Priority: MC > YUV Generator > ME > SRAM > DCT > Predictor > Q . . . Sample Application

13. Placement Sample Application

14. Experimental Results

15. Extension to 3D NoCs Cosideration of TSV features Future Work

16. THANKS!