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GRAND Perspectives of graphene electronics. Heinrich Kurz Advanced Microelectronic Center Aachen, AMO GmbH Institute of Semiconductor Electronics at RWTH Aachen University. 22 nm. 32 nm. DESIGN. 45 nm. 65 nm. 90 nm. Evolution vs. Revolution of Moore. SETs. Organic Computing.

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Grand perspectives of graphene electronics

GRANDPerspectives of graphene electronics

Heinrich Kurz

Advanced Microelectronic Center Aachen, AMO GmbH

Institute of Semiconductor Electronics at RWTH Aachen University

Evolution vs revolution of moore

22 nm

32 nm


45 nm

65 nm

90 nm

Evolution vs. Revolution of Moore


Organic Computing



Beyond CMOS

More than Moore



  • - ballistic transport

  • - photonics

  • - C-interconnects

  • THz-transistor

  • non-silicon

  • graphene

  • parallel processing

  • - MEMS

  • - sensors

  • - RF

  • - System-on-Chip

  • - power electronics

  • polymer

More Moore

Hype cycles gartner
Hype Cycles - Gartner

Case Study Nanotechnology

Valid foranyhighlycompetitivetechnologyfield


Positive Hype




Negative Hype






The essence of graphene
The essence of Graphene





H Hamiltonian (Energy), m*effective mass, p momentum

vFFermi-velocity, c speed of light, σ Pauli matrices

from A.K. Geim, Science 324,1530 (2009)

Carbon and cmos 4 layer problem
Carbon and CMOS: 4 - layer problem

  • Passivation

  • Exclusion of atmospheric influences



  • Dielectric

  • Same as for bottom SiO2

  • Dielectric constantk

  • Leakage current

  • Electrotransport through dielectric




Dielectric (SiO2)

  • Contacts

  • Contact resistance

  • Metall induced doping

  • Fermi level shift

Backgate (Si)

Interface SiO2 – Graphene

  • Interface traps

  • Surface termination

  • Bonding

  • Surface roughness

  • water

  • → mobility degradation, doping

  • Graphene

  • Relaxed, unrelaxed, strain

  • p,n puddles

  • Edge orientation/termination

  • Unintentional hydrogenation (e.g. HSQ)

  • Influence of oxygen during etching

Grand overall objectives
GRAND: Overall objectives

  • Explore the potential of graphene for ICT

  • Fabrication and simulation of switches (RF, FET, TFET, Sensors) and interconnects at the nanoscale.

  • Can graphene fulfil its promise of taking CMOS to the “Beyond CMOS” era?

Grand partners
GRAND partners


Device fabrication


Graphene based

FETs and interconnects


Graphene Synthesis



Grand overall objectives1
GRAND: Overall objectives

Advantages of graphene based devices

  • High carrier mobility (>10.000 cm²/Vs at RT)

  • High current carrying capability (>108 A/cm²)

  • Ultimately thin, ultimate incarnation of the surfaces

  • p- and n-type behavior nearly symmetric

    Challenges for realizing graphene based FETs

  • Introducing a band gap (and preserve carrier mobility)

    (target: Ion/Ioff>104)

  • Wafer-scale synthesis of graphene

Grand perspectives of graphene electronics

Graphene FETs

  • Three concepts for introducing a band gap:

  • Graphene nanoribbons

  • Bilayer Graphene with I electric field

  • Doping of graphene (replacing C-atoms)

Experimentally realized yet

Graphene nanoribbons
Graphene nanoribbons

Simulation (TB) of perfect 3.3 nm GNR FETs

Na = 28 W = 3.3 nm (Eg = 0.41 eV)

doxid = 2 nm

ION/IOFF > 104 can be achieved with W = 3.3 nm

R. Grassi et al., J. Comp. Elect. 8, 441 (2009)

Graphene nanoribbons1
Graphene nanoribbons

GNR fabricated by lithography



W ~ 20nm


  • Resistance increases with decreasing T: Energy gap!

AMO unpublished

Grand perspectives of graphene electronics

Graphene nanoribbons

  • Pro:

  • On/off ratios >104 achievable for w < 4 nm

  • Contra:

  • Mobility limited to values < 1.000 cm²/Vs

  • Edge-roughness dominates transport in devices

  • Width must be controlled with atomic precision

Bilayer fet
Bilayer FET

Symmetry breaking by vertical E-field

introduces gap in bilayer graphene:


Two gates required to vary EG and EF

Bilayer fet1
Bilayer FET

Consequences for band gap in bilayer graphene:

Always a conducting path; band gap not visible in transport.

Scanning gate microscopy
Scanning gate microscopy

Allows local mapping of charge neutrality point

M.R. Connolly et al., APL 96, 113501 (2010)

Scanning gate microscopy1
Scanning gate microscopy

Variation of the CNP in a graphene flake

CNP at gm/G=0

M.R. Connolly et al., APL 96, 113501 (2010)

Bilayer fet2
Bilayer FET

Possible solutions:

Reducing inhomogenities

e.g. by functionalization

Patterning to w<~200 nm

Realized by CMOS

compatible processes

Bilayer fet3
Bilayer FET

Bilayer graphene FET

w = 50 nm, l = 200 nm

B.N. Szafranek et al., APL 96, 112103 (2010)

Bilayer fet4
Bilayer FET


Wolpertinger 1.2


w = 50 nm

l = 200 nm

25 nm SiOx

Dmax / ε0 = 1.6 V/nm at UBG = 40V and UTG = -4.5V

B.N. Szafranek et al., APL 96, 112103 (2010)

Bilayer fet5
Bilayer FET

Characteristic parameters at RT

Wolpertinger 1.2

[1] Jiao et al., Nature 458, 877 (April 2009)

* EG determined by RDP – D relation

Bilayer fet6
Bilayer FET

Bilayer graphene TFET (TB-Simulations)

tBG = tTG = 3 nm (SiO2)

Emax = 1.3 V/nm

  • Small slope switches possible with bilayer graphene

G. Fiori et al., IEEE Device Lett. 30, 1096 (2009)

Grand perspectives of graphene electronics

Bilayer FET

  • Pro:

  • On/off ratios >104 possible with TFETs

  • Mobility of ~1.000 cm²/Vs already achieved

  • Mobility > 5.000cm²/Vs possible

  • Contra:

  • Device fabrication is more complex

Grand perspectives of graphene electronics


  • Route for realizing bilayer tunnel FETs:

  • Further reduction of charge inhomogenities

  • Advanced dielectric deposition

  • Controlled doping


by Tyndall

Grand perspectives of graphene electronics


Self assembled monolayer for functionalization of graphene

Tyndall to be published

Grand perspectives of graphene electronics


Functionalization reduces inhomogenities without annealing

Confirmation by scanning gate microscopy needed.

Tyndall to be published

Grand perspectives of graphene electronics


  • Routes for realizing graphene based FETs

  • explored theoretically and experimentally:

  • Graphene nanoribbon FETs show promising on/off

  • ratios for w<4 nm.

  • Draw backs: Low mobility and currently not realizable.

  • Bilayer tunneling FETs are a promising route for low-

  • power application.

  • Advantages: Experimentally already realizable and high

  • mobility.

Thanks to
Thanks to

C.G. Smith

M.R. Connolly

D. Neumaier

B.N. Szafranek

D. Schall

M. Baus

S. Roche

T. Poiroux


  • Quinn

  • B. Long

  • M. Manning

  • G. Visemberga


G. Baccarani

A. Gnudi

E. Sangiorgi

S. Reggiani


M. Macucci

G. Iannaccone

G. Fiori


L. Selmi

P. Palestri

D. Esseni

M. Bresciani