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A R educed S witch C ount 5- L evel I nverter W ith C ommon-Mode V oltage E limination and capacitor voltage bala

A R educed S witch C ount 5- L evel I nverter W ith C ommon-Mode V oltage E limination and capacitor voltage balancing For an O pen-End W inding IM D rive. Gopal Mondal Centre for Electronics Design and Technology Indian Institute of Science, Bangalore INDIA: 560012.

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A R educed S witch C ount 5- L evel I nverter W ith C ommon-Mode V oltage E limination and capacitor voltage bala

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  1. AReduced Switch Count 5-Level Inverter With Common-Mode Voltage Elimination and capacitor voltage balancing For an Open-End Winding IMDrive Gopal Mondal Centre for Electronics Design and Technology Indian Institute of Science, Bangalore INDIA: 560012 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  2. Multi-level inverters Previous work Motivation Proposed Scheme Implementation of the proposed Scheme Experimental Results DC-link capacitor voltage balancing an open loop control scheme Implementation of the Closed loop capacitor voltage balancing Experimental Results Speed Reversal Flow of presentation CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  3. Multi-level inverters CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  4. Multi-level inverters are the preferred choice in industry for the application in High voltage and High power application Advantages of Multi-level inverters Higher voltage can be generated using the devices of lower rating. Increased number of voltage levels produce better voltage waveforms and reduced THD. Switching frequency can be reduced for the PWM operation. Multi-level inverters CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  5. Previous work A five-level inverter for the open end winding IM drive The 5-level inverters (Inverter-I and Inverter-II) at both the end of the open end winding induction motor are realised by cascading two 2-level inverters and one 3-level (NPC) inverter. Fig.-1 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  6. Previous work space vector locations for inverter-I or inverter-II For each inverters (inverter-I and inverter-II) total 125 switching states available which are distributed over the 61 voltage vector points creating a 5-level voltage vector structure Fig.-2 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  7. Previous work Combined voltage space vector structure of a dual five-level inverter fed open-end winding induction motor drive Combined voltage vectors of inverter-I and inverter-II giving a 9-level voltage vector structure. There are 15625 switching states distributed over 217 voltage space vector point. Fig.-3 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  8. Because of the common DC- sources at both end of the inverters, there will be circulating current called the common mode current due to the common mode voltage. CMV for inverter-I is defined as VCMA = (VAO + VBO + VCO) / 3. (1) CMV for inverter-II’ is defined as VCMA’ = (VA’O’ + VB’O’ + VC’O’) / 3. (2) Equivalent common-mode voltage for the combined inverter system (CMV generated at the inverter phases) is VCM = VCMA – VCMA’ If the nine level voltage vector is generated without common mode voltage, there are 8 DC sources required instead of four. Previous work Common mode voltage (CMV) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  9. PWM inverters generate high frequency, high amplitude common mode voltages, which induces ‘shaft voltage’ on the rotor side When the induced shaft voltage exceeds the breakdown voltage of the lubricant in the bearings, result in large bearing currents This damages the bearings, leading to motor failures and also causes EMI PWM inverters which do not generate common mode voltage are suggested as a solution to the above problems Previous work Common mode voltages and its effects CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  10. Previous work Voltage vectors with zero common mode voltage for the inverter-I and Inverter-II To eliminate the common mode voltage only those switching states has zero common mode voltage are chosen for the PWM switching. 19 voltage vectors with 19 switching states has zero common mode voltage. Switching states with zero common mode voltage Produce a 3-level voltage space vector structure Fig.-4 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  11. Combination of the two three-level voltage space vector structure will give a five-level structure. There are 361 switching states distributed over 61 voltage vector points Previous work Combined voltage vector structure of inverter-I and Inverter-II Fig.-5 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  12. The power circuit uses total 48 switches. Redundant switching states are used for the common mode voltage elimination and closed loop DC-link capacitor voltage balancing. Number of voltage sources can be reduced and two voltage sources are enough with four DC-link capacitors to implement the five level voltage waveform. Previous work CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  13. Previous work The reduced power circuit with less number of voltage sources is- CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  14. Previous work Fig.-6 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  15. There are 361 switching statesavailable for 61 voltage space vector locations for the five level inverter discussed. But only few are used for the common mode voltage elimination and DC-link capacitor voltage balancing. It implies that the number of redundant switching states can be reduced keeping the performance of the inverter same. It is observed that by reducing the power circuit structure it is possible to maintain the same performance of the inverter. Motivation CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  16. Proposed Scheme The propose power circuit of the five-level inverter for open-end winding induction motor drive Fig.-7 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  17. The five-level inverters (Inverter system-A and Inverter system-A’) are realised by cascadingTwo 2-level and a three-level inverters. Two 2-level inverters are common to both the inverter system-A and Inverter system-A’ Proposed Scheme The propose power circuit of the 5-level inverter Fig.-7b CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  18. Proposed Scheme The propose power circuit of the five-level inverter for open-end winding induction motor drive Complementary Switches for leg-A of inverter system-A: S11 and S14 S21 and S34 S31 and S24 S41 and S44 Similar for the other phases Fig.-7a CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  19. Due to the power circuit structure some of the available redundant switching states are reduced, but the available switching states are sufficient for the common mode elimination and DC-link capacitor voltage balancing. Proposed Scheme The propose power circuit of the 5-level inverter Fig.-7b CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  20. Proposed Scheme Combined voltage space vector locations for 5-level inverter with zero common mode voltage Fig.-7c CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  21. Proposed Scheme Combined voltage space vector for 5-level inverter with zero common mode voltage Fig.-7c CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  22. Proposed Scheme Combined voltage space vector for 5-level inverter with zero common mode voltage Switching states for the voltage vector A1’ (-101,-202), (10-1,000), (000,-101), (20-2,10-1), (01-1,-110), (02-2,-12-1), (0-11,-1-12), (-12-1,-220), (11-2,01-1), (1-10,0-11), (1-21,0-22), (2-1-1,1-10), (-110,-211), (2-20,1-21) Fig.-7c CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  23. Proposed Scheme Some of the switching states are impossible for Fig-II Switching state(2-1-1,1-10) possible Switching state (2-1-1,1-10) impossible Fig.-I. Previous power circuit Fig.-II. Proposed power circuit Fig.-7d CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  24. Previous Scheme Combined voltage space vector for 5-level inverter with zero common mode voltage Switching states for the voltage vector A1’ (-101,-202), (10-1,000), (000,-101), (20-2,10-1), (01-1,-110), (02-2,-12-1), (0-11,-1-12), (-12-1,-220), (11-2,01-1), (1-10,0-11), (1-21,0-22), (2-1-1,1-10), (-110,-211), (2-20,1-21) Fig.-7c CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  25. Proposed Scheme Combined voltage space vector for 5-level inverter with zero common mode voltage Switching states for the voltage vector A1’ (-101,-202), (10-1,000), (000,-101), (20-2,10-1), (01-1,-110), (02-2,-12-1), (0-11,-1-12), (-12-1,-220), (11-2,01-1), (1-10,0-11), (1-21,0-22), (2-1-1,1-10), (-110,-211), (2-20,1-21) Fig.-7c CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  26. Number of redundant switching states are less for this power circuit compared to the previous one(361). There are 241 switching states possible for The present scheme(61 voltage space vector locations) But the available switching states are sufficient for the common mode voltage elimination and DC-link capacitor voltage balancing Proposed Scheme The propose power circuit of the 5-level inverter Fig.-7e CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  27. Common mode voltage is eliminated by selecting the switching states which have zero common mode voltage. Switching states are selected in such a way, that the pole voltage have the half-wave symmetry and there is no even harmonics in both pole and phase voltages Proposed Scheme Selection of the Switching states for the elimination of common mode voltage Fig.-8 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  28. Proposed Scheme Speed control scheme A simple V/f control is used for the implementation of the proposed five-level inverter. The PWM strategy is automatically calculating the switching time for the voltage vectors and the switching states are selected from the look up table in the FPGA. CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  29. (a) Simulation result (b) experimental result Fig.9(a),(b): top and bottom are Pole voltages VOA andVOA’ and the middle one is machine phase voltage VAA’ for switching the inner Sectors. [Y-axis: 1div=50V, X-axis: 1div=0.02 sec] Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  30. (a) Simulation result (b) experimental result [Y-axis: 1div=50V,1div=1A, X-axis: 1div=0.01 sec] [Y-axis: 1div=50V, 1div=5A, X-axis: 1div=0.02 sec] Fig.10(a),(b): Phase voltage and phase currentfor switching the inner Sectors. Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  31. (a) (b) Fig.11(a),(b): [Y-axis: normalized amplitude, X-axis: order of harmonics] Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  32. (a) Simulation result (b) experimental result Fig.12(a),(b): top and bottom are Pole voltages VOA andVOA’ and the middle one is machine phase voltage VAA’ for three-level of operation [Y-axis: 1div=50V, X-axis: 1div=0.02 sec] Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  33. (a) Simulation result (b) experimental result [Y-axis: 1div=50V,1div=1A, X-axis: 1div=0.01 sec] [Y-axis: 1div=50V, 1div=5A, X-axis: 1div=0.02 sec] Fig.13(a),(b): Phase voltage and phase currentfor three-level of operation. Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  34. (a) (b) Fig.14(a),(b): [Y-axis: normalized amplitude, X-axis: order of harmonics] Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  35. (a) Simulation result (b) experimental result Fig.12(a),(b): top and bottom are Pole voltages VOA andVOA’ and the middle one is machine phase voltage VAA’ for four-level of operation (a) [Y-axis: 1div=50V, X-axis: 1div=0.02 sec] (b) [Y-axis: 1div=50V, X-axis: 1div=0.01 sec] Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  36. (a) Simulation result (b) experimental result [Y-axis: 1div=50V,1div=1A, X-axis: 1div=0.02 sec] [Y-axis: 1div=50V, 1div=5A, X-axis: 1div=0.01 sec] Fig.13(a),(b): Phase voltage and phase currentfor four-level of operation. Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  37. (a) (b) Fig.14(a),(b): [Y-axis: normalized amplitude, X-axis: order of harmonics] Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  38. (a) Simulation result (b) experimental result Fig.12(a),(b): top and bottom are Pole voltages VOA andVOA’ and the middle one is machine phase voltage VAA’for five-level of operation [Y-axis: 1div=50V, X-axis: 1div=0.005 sec] Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  39. (a) Simulation result (b) experimental result [Y-axis: 1div=50V,1div=1A, X-axis: 1div=0.01 sec] [Y-axis: 1div=50V, 1div=5A, X-axis: 1div=0.01 sec] Fig.13(a),(b): Phase voltage and phase currentfor five-level of operation. Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  40. (a) (b) Fig.14(a),(b): [Y-axis: normalized amplitude, X-axis: order of harmonics] Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  41. DC-link capacitor voltage balancing CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  42. With Proper DC link capacitor balancing the four DC-link voltage sources can be reduced to TWO DC-link capacitor voltage balancing CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  43. DC-link capacitor voltage balancing Fig.16. Reduced power circuit with capacitor voltage balancing CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  44. Two switching states are selected at locations for DC link balancing along with common mode voltage elimination, The selected two switching states at a particular location has opposite effect on DC link capacitor balancing So in Two sampling periods the DC link capacitor charges balance can be achieved In locations where there is no effect on the DC-link capacitors, only one switching state is used for CME DC-link capacitor voltage balancing- an Open loop control scheme CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  45. DC-link capacitor voltage balancing- an Open loop control scheme Two switching states for the same voltage vector Motor phase connections for different switching states Fig.-17 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  46. DC-link capacitor voltage balancing- an Open loop control scheme Current through C4:iC+iA C3:iA C2:iC C1:iC+iA Two switching states for the same voltage vector Current through C4:iC+iA C3:iC C2:iA C1:iC+iA Fig.-17 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  47. After two switching interval total current through C4:2*(iC+iA) C3: iC+iA C2: iC+iA C1:2*(iC+iA) =>Vc4 = Vc1 and Vc2 = Vc3 (000,-101) and (10-1,000) are complementary pairs DC-link capacitor voltage balancing- an Open loop control scheme CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  48. DC-link capacitor voltage balancing- an Open loop control scheme Switching state with no effect on DC-link capacitor voltages Current through C4:iC+iA C3:0 C2:0 C1:iC+iA =>Vc4 = Vc1 and Vc2 = Vc3 Fig.-18 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  49. DC-link capacitor voltage balancing- an Open loop control scheme Fig.-19. (a) Voltage and current waveform for the operation of the motor From zero speed to the 5-level of operation CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

  50. Open loop capacitor voltage balancing works well for the ideal conditions. For any abnormal conditions like Sudden short circuit, Asymmetry in PWM pulses, Unequal DC-link capacitors etc. Closed loop capacitor voltage balancing is required DC-link capacitor voltage balancing CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

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