Power Electronic Devices

1. Power Supply Systems Electrical Energy Conversion and Power Systems Universidad de Oviedo Power Electronic Devices Semester 1 Lecturer: Javier Sebastián

2. Outline • Review of the physical principles of operation of semiconductor devices. • Thermal management in power semiconductor devices. • Power diodes. • Power MOSFETs. • Power IGBTs • High-power, low-frequency semiconductor devices (thyristors).

3. Electrical Energy Conversion and Power Systems Universidad de Oviedo Lesson 4 - Power MOSFET. Semester 1 - Power Electronic Devices

4. Outline • The main topics to be addressed in this lesson are the following: • Review of the basic structure and operation of low-power MOSFETs. • Internal structures of power MOSFETs. • Static characteristics of power MOSFETs. • Dynamic characteristics of power MOSFETs. • Losses in power MOSFETs.

5. S G D Ohmic contact SiO2 D S Metal Metal G Oxide Semiconductor N+ N+ P- + Substrate D • Schematic symbol D (Drain) Substrate G G (Gate) P-channel enhancement MOSFET S S (source) N-channel enhancement MOSFET Review of the basic structure of low-power MOSFETs. Structure Name Schematic symbol

6. G S D Depletion layer (space charge) - - - - • - - - - N+ N+ V1 P- - - + + + + + Substrate G S D A thin layer containing mobile electrons (minority carriers) is induced +++ +++ ++ ++ - - - - N+ N+ P- + Substrate Review of the operation of low-power MOSFETs (I). + + + + V2 > V1

7. This thin layer containing mobile electrons (minority carriers) is called inversion layer G S D ++++ ++++ - - - - N+ N+ - - - - P- V3 = V TH > V2 + This is a depletion layer (without carriers) Substrate Review of the operation of low-power MOSFETs (II). • When the electron concentration in the new thin layer of electrons is the same as the hole concentration in the substrate, we say that the inversion process has started. • The gate voltage corresponding to this situation is the threshold voltage, VTH. • It should be noted that the inversion layer is like a new N-type region artificially created by the gate voltage.

8. G • Inversion layer when the voltage between gate and substrate is higher than VTH. D S +++++ +++++ - - - - - - N+ N+ - - - - P- V4 > V TH vDS iD P Substrate G D S +++++ +++++ vGS - - - - - - N+ N+ - - - - P- Substrate Review of the operation of low-power MOSFETs (III). • Now, we connect terminal source to terminal substrate. • Moreover, we connect a voltage source between terminals drain and source. • Howis the drain current iD now?

9. vDS= vDS1 > 0 iD G S D +++++ +++++ vGS - - - - - N+ N+ - - - - - P- Substrate Review of the operation of low-power MOSFETs (IV). • Now, there is a N-type channel due to the inversion layer. • This channel allows the current to pass from the drain terminal to the source terminal. • With low values of vDS (i.e.,vDS<< vGS), the channel shape is uniform. • If the value of vDS approaches vGS, then the channel shape is not uniform any more. • This is the normal situation when the MOSFET is working in linear applications, which is very different from the case of switching applications.

10. vDS2 > vDS1 vDS1 iD» 0 iD» 0 G S D S G D N+ N+ N+ N+ P- P- Substrate Substrate Review of the operation of low-power MOSFETs (V). • Operation whenvGS = 0. • Drain current iD is practically zero whenvGS = 0, because no channel exists between drain and source. • The same occurs for any vGS < VTH (i.e., iD» 0).

11. iD 2.5kW iD[mA] 4 vGS= 4.5V D + G vDS vGS = 4V 10V S 2 + - vGS= 3.5V vGS - vGS = 3V vGS = 2.5V vGS < VTH = 2V 0 12 vDS [V] 8 4 Resistive behaviour Behaviour as current source Open-circuit behaviour Review of the operation of low-power MOSFETs (VI) • Graphical analysis. Load line < 4.5V VGS = 0V < 2.5V < 3V < 3.5V < 4V

12. S G D N+ N+ P- + Substrate D G S Review of the operation of low-power MOSFETs (VII) • Parasitic diode. • There is a parasitic diode between drain terminal and source terminal due to the internal connection between substrate and source.

13. S G D Internal structure of power MOSFETs (I). • A typical transistor is constituted of several thousand cells. • As all the FET devices, MOSFET can be easily connected in parallel. • They are vertical MOSFETs. • Examples of cells: Gate Source Source Gate Source-body connection N+ N+ N+ P P N- N- Body Body N+ N+ Drain Drain V-grooveMOS (VMOS) DoublediffusedMOSFET (DMOS)

14. Internal structure of power MOSFETs (II). • Other structures (I): Source Source N+ N+ P P Gate Gate N- N- Source-body connection N+ N+ Body Body Drain Drain MOSFET with trench gate (UMOSFET) MOSFET with extending trench gate (EXTFET) • The breakdown voltage is limited to 25 V.

15. Internal structure of power MOSFETs (III). • Other structures (II): Source Doping Source-body connection ND-source Source NA-body Gate N+ Source-body connection P ND-drain- Gate N ND-drain+ N+ N+ N+ P+ Drain Body N- Body P- Drain MOSFET with graded doped (GD) andtrench gate Structure with charge coupled PN super-junction in the drift region (CoolMOSTM) N+ • Also for low voltage (breakdown voltage is about 50 V). • 3 times better for 600-800 V devices.

16. Internal structure of power MOSFETs (IV). • Tridimensional structure of a DMOS: Gate Source Drain N+ N+ Drift region P Body N- N+

17. RDS(on) = 12 mW, ID = 57 A RDS(on) = 9.4 mW, ID = 12 A RDS(on) = 9 mW, ID = 93 A RDS(on) = 1.5 mW, ID = 240 A RDS(on) = 5.5 mW, ID = 86 A Packages for power MOSFETs (I). • Packages are similar to those of power diodes (except axial leaded through-hole packages). • There are many different packages. • Examples: 60VMOSFETs.

18. RDS(on) = 3.4 mW, ID = 90 A Packages for power MOSFETs (II). • Other examples of 60VMOSFETs.

19. Information given by the manufacturers. • Static characteristics: • - Drain-source breakdown voltage. • - Maximum drain current. • - Drain-source on-state resistance. • Gate threshold voltage. • Maximum gate to source voltage. • Dynamic characteristics: • - Parasitic capacitances.

20. Drain-source breakdown voltage, V(BR)DSS. • It is the drain-source breakdown voltage when the gate terminal is connected to the source terminal. • It corresponds to a specific value of the drain current (for example, 0.25 mA). ID = 0.25 mA D G • V(BR)DSS S

21. Maximum drain current. • Manufacturers provide two different values (at least) : - Maximum continuous drain current, ID. • - Maximum pulse drain current, IDM. • IDdependsonthemounting base (case) temperature. • At 100 oC, ID = 23·0.7 = 16.1 A

22. Drain-source on-state resistance, RDS(ON) (I). • It is one of the most important characteristics in a power MOSFET. The lower, the better. • For a given device, its on-resistance decreases with the gate voltage, at least until this voltage reaches a specific value. • PowerMOSFETs typically increase their on-resistance with temperature. Under some circumstances, power dissipated in this resistance causes more heating of the junction, which further increases the junction temperature, in a positive feedback loop. • If a MOSFET transistor produces more heat than the heat sink can dissipate, then thermal runaway can still destroy the transistors. This problem can be alleviated by lowering the thermal resistance between the transistor die and the heat sink. • Thermal runaway refers to a situation where an increase in temperature changes the conditions in a way that causes a further increase in temperature, often leading to a destructive result. It is a kind of uncontrolled positive feedback. • However, the increase of on-resistance with temperature helps balance current across multiple MOSFETs (and MOSFET cells) connected in parallel, so current hogging does not occur.

23. Drain-source On Resistance, RDS(on) (Ohms) Drain-source on-state resistance, RDS(ON) (II). • RDS(ON) increases with temperature. • RDS(ON) decreases with VGS.

24. Drain-source on-state resistance, RDS(ON) (III). • Comparing different devices with a given value of ID, the value of RDS(on) increases with V(BR)DSS.

25. Drain-source on-state resistance, RDS(ON) (IV). • The use of new internal structures (such ascharge coupled PN super-junction in the drift region) has improved the value of RDS(ON) in devices in the range of 600-1000 V. Year1984 • Year 2000

26. Gate threshold voltage, VGS(TO) (I). • Manufacturers define VGS(TO) with the gate terminal connected to the drain terminal and at a specific value of ID (e.g., 0.25 mA or 1 mA) • Standard values of VGS(TO) are in the range of 2-4 V. ID = 1 mA D G • VGS(TO) S

27. Gate threshold voltage, VGS(TO) (II). • VGS(TO) depends on the temperature:

28. Maximum gate to source voltage, VGS. • Frequently,this value is ± 20V.

29. D Cdg Cds G S Cgs Parasitic capacitances in power MOSFETs (I). • Power MOSFETs are faster than other power devices (such as bipolar transistors, IGBTs, thyristors, etc.). • This is because MOSFETs are unipolar devices (no minority carriers are stored at the edges of PN junctions). • The switching speed is limited by parasitic capacitances. • Three parasitic capacitances should be taken into account: - Cgs, which is a quite linear capacitance. • - Cds, which is a non-linear capacitance. • - Cdg, Miller capacitance, which is also a non-linear capacitance.

30. D D Ciss Coss Cdg Cdg Cds Cds G G S S Cgs Cgs Parasitic capacitances in power MOSFETs (II). • Manufacturers provide information about three capacitances, which are different from the ones mentioned in the previous slide (however, they are directly related with them): • - Ciss = Cgs + Cgd withVds=0 (input capacitance). Ciss»Cgs. • - Crss = Cdg(Miller or feedback capacitance). • - Coss = Cds+ Cdg (output capacitance). Coss»Cds.

31. Parasitic capacitances in power MOSFETs (III). • Example of information provided by manufacturers. Ciss = Cgs + Cgd Crss = Cdg Coss = Cds+ Cdg

32. IL Cdg V2 Cds V1 R Cgs Switching process in power MOSFETs (I). • Analysis of the switching process assuming: - Inductive load (frequent situation in power electronics). - Clamping (or free wheeling) diode. - Ideal diode.

33. IL iD iDT Cdg V2 A vDG Cds V1 R + B + + Cgs - - - + + vGS vDS - - Switching process in power MOSFETs (II). • Starting situation: - The power transistor is off and power diode is on. - Therefore: • vDG = V2, vDS = V2 andvGS = 0. • iDT = 0 and iD = IL. - From this situation, the mechanical switch changes from position “B” to “A”.

34. vGS B®A VGS(TO) • This slope depends on R, Cgs andCdg. vDS V2 IL iDT iD IL vDG + iDT Cdg - + + + A V2 - - - + Cds V1 + R B vDS vGS Cgs - - Switching process in power MOSFETs (III). • iDT = 0 while vGS < VGS(TO) • vDS = V2 whileiDT < IL (the diode is on).

35. vGS B®A VGS(TO) vDS iDT IL + + + - - - + vDS - Switching process in power MOSFETs (IV). • The current provided by V1 through R is mainly used to discharge CdgÞ almost no current is used to charge CgsÞvGS = constant. • As a consequence, the Miller plateau appears. IL vDG iDT + Cdg - A V2 Cds V1 + R B vGS Cgs -

36. vGS V1 B®A VGS(TO) The time constant depends on R, Cgs and Cdg. vDS IL iDT IL vDG + iDT Cdg + + - - - A + V2 Cds V1 + R vDS B vGS Cgs - - Switching process in power MOSFETs (V). • Cgs y Cdgcomplete the charging process.

37. V1 vGS B®A VGS(TO) vDS iDT IL iDT Cdg + t2 t3 t0 t1 V2 + + PVI - - - + + Cgs Cds vDS vGS - - Switching process in power MOSFETs (VI). • Computing losses between t0 and t2: • - The control voltage source V1 has to charge Cgs (large) from 0 to VM and discharge Cdg (small) from V2 to V2-VM. -There is high voltage (V2) and increasing current (from 0 to IL) in the MOSFET at the same time (fromt1to t2). VM

38. vGS V1 B®A VM VGS(TO) vDS iDT = IL iDT IL Cdg t2 t3 t0 t1 + + + IL PVI - - - + + Cds Cgs vDS vGS - - Switching process in power MOSFETs (VII). • Computing losses between t2 and t3: • - The control voltage source V1 has to discharge Cdg from V2-VM to -VM. • - There is high current (IL) and decreasing voltage (from V2 to 0) in the MOSFET at the same time (from t2 to t3).

39. vGS V1 B®A VM VGS(TO) vDS iDT = IL iDT IL Cdg t2 t3 t0 t1 + + + IL PVI - - - + + Cds Cgs vDS vGS - - Switching process in power MOSFETs (VIII). • Computing losses after t3: • - The control voltage source V1 has to charge Cgs from VM to V1 and Cdg from -VM to -V1. • - There is high current (IL), but the voltage is very low. Therefore, there are only conduction losses.

40. Qgd Qgs vGS t2 t3 t0 Qg iV1 iV1 R V1 Switching process in power MOSFETs (IX). • The switching speed strongly depends on the gate chargeQg. The gate charge is the electric charge that the driving circuitry must provide for switching the MOSFET. • - The driving circuitry must provide the gate-source chargeQgs from t0to t2. • - The driving circuitry must provide the gate-drain chargeQgd from t2 to t3. • - The driving circuitry must provide more electric charge for the gate voltage to reach the final value V1. The gate charge Qg includes this charge and the addition of Qgs + Qgd. - For a given driving circuitry, the lower Qg, the faster the switching process. - Obviously, t2-t0»QgsR/V1, t3-t2»QdgR/V1 and PV1 = V1QgfS, where fS is the switching frequency.

41. IRF 540 • Year 1984 BUZ80 Year2000 Switching process in power MOSFETs (X). • Example of information provided by manufacturers:

42. Power losses in power MOSFETs (I). • Static losses: • Reverse losses Þ negligible in practice due to the low value of the drain current at zero gate voltage, IDSS. • Conduction losses, due to RDS(on): • PMOS_cond = RDS(ON)·ID_RMS2, • where ID_RMS is the RMS value of the drain current. • Switching (dynamic) losses: • Turn-on losses and turn-off losses. • Driving losses.

43. Switchinglosses Won Conductionlosses Woff Power losses in power MOSFETs (II). vGS vDS PMOS_cond = RDS(on)·ID_RMS2 PMOS_S = fS(won + woff) iDT PVI

44. iV1 Qgd V1 Qgs vGS Equivalent circuit RB t2 t3 t0 Qg iV1 iV1 V1 R Actual circuit to have low R equivalent values Power losses in power MOSFETs (III). • Driving losses. PV1 = V1QgfS • It should be noted that for a given MOSFET, the switching times decrease when R decreases, thus allowing higher values of iV1. • Moreover, the lower the switching times, the lower the switching losses.

45. IRF 540 D G S The parasitic diode in power MOSFETs (I). • It usually is a slow diode, especially in the case of high voltage MOSFETs.

46. The parasitic diode in power MOSFETs (II). • Case ofa highvoltageMOSFET structure (e.g., charge coupled PN super-junction in the drift region).