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THERMINATOR Modeling, Control and Management of Thermal Effects in Electronic Circuits of the Future. Kick-Off Meeting Catania – February 26, 2010. Agenda, February 26 th 2010. 09:00 Welcome and Project highlights S. Rinaudo Round-table and presentation of each partner

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therminator modeling control and management of thermal effects in electronic circuits of the future

THERMINATORModeling, Control and Management of Thermal Effects in Electronic Circuits of the Future

Kick-Off Meeting

Catania – February 26, 2010

agenda february 26 th 2010
Agenda, February 26th 2010

09:00 Welcome and Project highlightsS. Rinaudo

Round-table and presentation of each partner

10:00 Technical Work Plan walk-through E. Macii

Deploy the operative workplan (part 1)

Milestones, Deadlines, Gantt Discussion and Agreement of Project Handbook

Scheduling the main governance’s Meetings

11:30 Project management overview and IPR G. Gangemi

Project Management structure and Handbook

IPCA and IPs

11:45 Training Workplan N. Gergely

12:00 Deploy the operative workplan (part 2) E. Macii

R&D, Roadmap, dissemination

12:30 Lunch Break

13:30 Deploy the operative workplan (part 3) E. Macii

Technical dependencies and links among partners

16:00 THERMINATOR Management issues R. Zafalon

Press Release: draft preparation (To issue by April 2010)

Pending issues to be agreed

Money transferring policy from coordinator’s account to partners

17:30 Final Wrap-up & Action Items

project overview

Project Overview

E. Macii (POLITO)

objectives and consortium
Objectives and Consortium

The Consortium

The Objectives

  • Development of new modeling and simulation capabilities.
  • Development of new thermal-aware design techniques, methodologies and prototype tools
  • Validation of thermal model accuracy against silicon measurements
  • Assessment of results of application of thermal-aware design solutions on test-chips.
  • Assessment of results of application of thermal-aware EDA prototype tools on industry-strength design cases.

STM, NXP, IFX

IC Vendors

BME, CSEM, FHG,

IMEC, CEA-LETI, OFFIS,

POLITO, UNIBO

ResearchInstitutes

CV,GDA,MUN,SNPS

EDAVendors

15 partners

therminator platform

Packageselection

Thermal-Aware design exploration

System-level thermal modeling and simulation

systems

Architecture-level Thermal modeling

Thermal Interconnect modeling

Block-level thermalmodelling and simulation

blocks orcomponents

Thermal

Management of digital blocks

Thermal compensation for interconnects

ThermalModeling

and

Thermal-AwareSimulation

Package thermal modeling

Thermal-AwareSynthesis

Thermal-AwareDesign Using Advanced Technologies

Circuit-level thermal modeling and simulation

Logi-ThermalSimulation

circuits

Temperature-InsensitiveLibrary

devices

Device Characterization and Thermal Compact Modeling

discrete

analog/RF

digital

Simulation, Modeling

Design

Exploration

Therminator Platform
workplan

WP1: Technology Characterization, Tool Requirementsand Test Case Identification

WP2: Process, Device and Compact Modeling

WP3: Modeling,Simulation andDesign of Digital Blocks

WP4: Modeling andSimulation of Analog/RFBlocks

WP5: Modeling andSimulation of DiscreteComponents

WP6: Package/System Modeling andDesign Exploration under Ambient Influence

WP7: Validation, Demonstration and Evaluation

WP8: Dissemination, Training,Exploitation and Roadmapping

RTD

DEM

WP9: Project Management

MGT

Workplan

Start date: 01/01/10

Duration: 36 months

Cost: 11 M€

EC funding: 6.4 M€

Effort: 944 p/m

gantt chart

WP1

T1.1 Technology characterization

Dx.y.1

Dx.y.2

Dx.y.3

Dx.y.4

Dx.y.5

Dx.y.6

Dx.y.7

Dx.y.8

Dx.y.9

Dx.y.10

Dx.y.11

T1.2 Tool requirements

T1.3 Test case identification

WP2

T2.1 Compact thermal modeling of new device structures and technologies

T2.2 Compact thermal modeling of CMOS devices for integrated circuits

T2.3 Physics-based compact thermal modeling for discrete devices

WP3

T3.1 Logi-thermal simulation methods and tools

T3.2 Thermal effects in digital circuit design for new CMOS technologies

T3.3 Logic design methodologies for temperature-insensitive circuits

T3.4 Monitoring circuits and design methodologies for thermal effect compensation

WP4

T4.1 Thermal modeling of analog/RF blocks

T4.2 Analog/RF circuit analysis in presence of high temperatures and on-chip thermal gradients

WP5

T5.1 Thermal modeling of discrete components

T5.2 Validation of modeling framework for discrete components

WP6

T6.1 Thermal description of the system package and ambient influence

T6.2 Thermal distribution in 3D SiP stacks and 2D SoCs

T6.3 System-level thermal-aware design

WP7

T7.1 Validation of models on silicon structures

T7.2 Demonstration of design techniques on test chips

T7.3 Evaluation of design methods and prototype tools on test cases

WP8

T8.1 Set-up and maintenance of project web-site

T8.2 Dissemination

T8.3 Training

T8.4 Exploitation and roadmapping

WP9

T9.1 Implementation of project management structures

T9.2 Project management

T9.3 IPR management

M0

M12

M24

M36

Gantt Chart
wp1 leader ifx
WP1 (Leader: IFX)

WP1: Technology Characterization, Tool Requirements and Test Case Identification

  • T1.1: Technology Characterization

Investigation and characterization of a wide collection of different nanoelectronic technologies and device architectures regarding temperature sensitivity and thermal effects

  • T1.2: Tool Requirements

Specification of the requirements for the EDA methodologies, tools and flows that will be developed within the project

  • T1.3: Test Case Identification

Identification by the semiconductor vendors of the test structures and of the test cases that will be used to assess the quality of the models, design solutions and EDA methodologies and prototype tools

wp2 leader ifx
WP2 (Leader: IFX)

WP2: Process, Device and Compact Modeling

  • T2.1: Compact thermal modeling of new device structures and technologiesDevelopment of methods for numerical simulation of devices that utilize new semiconductor structures and technologies, down to the 32/28nm process node.
  • T2.2: Compact thermal modeling of CMOS devices for integrated circuitsDevelopment of methods for numerical simulation of devices for integrated circuits implemented with traditional, state-of-the-art CMOS technologies.
  • T2.3: Physics-based compact thermal modeling for discrete devices

Development of methods for numerical simulation of devices for discrete semiconductor devices, specifically suitable for power converters and RF applications.

wp3 leader polito
WP3 (Leader: POLITO)

WP3: Modeling, Simulation and Design of Digital Blocks

  • T3.1: Logi-thermal simulation methods and tools

Generation of a logic/thermal co-simulator for the target technologies. This simulator will rely on thermal models of the basic design primitives (namely, logic gates, memory elements, interconnects).

  • T3.2: Thermal effects in digital circuit design for new CMOS technologies

Thermal efficiency comparison of different implementation of a test design using the new technologies and using traditional, state-of-the-art bulk CMOS technologies.

  • T3.3: Logic design methodologies for temperature-insensitive circuits

Investigation and development of innovative techniques, methodologies and prototype tools for thermal-aware synthesis.

  • T3.4: Monitoring circuits and design methodologies for thermal effect compensation

Investigation and development of innovative techniques, methodologies and prototype tools for thermal effect compensation, control and management.

wp4 leader nxp
WP4 (Leader: NXP)

WP4: Modeling and Simulation of Analog/RF Blocks

  • T4.1: Thermal modeling of analog/RF blocks

Since standard compact models, like those developed in the context of WP2, are not sufficient for such components, more accurate behavioral models are needed, which include also self heating effects. Therefore, electrical compact models have to be completed by model parts for the thermal behavior.

  • T4.2: Analog/RF circuit analysis in presence of high temperatures and on-chip thermal gradientsIn this Task, simulation-based methodologies to analyze and reduce the impact of thermal fluctuations on the behavior, yield or reliability of analog/RF blocks will be developed. In a first step, critical analog/RF components will be identified.
wp5 leader st
WP5 (Leader: ST)

WP5: Modeling and Simulation of Discrete Components

  • T5.1: Thermal modeling of discrete components

The objective of this task is the investigation and implementation of a modeling framework for discrete components.

  • T5.2: Validation of modeling framework for discrete components

The main objective of this Task is to validate the modeling framework of Task T5.1 through comparison of the data coming from camera-based analysis to those collected by application of the modeling methodology implemented inside the framework. Validation thus requires the implementation of one or more test cases,

wp6 leader nxp
WP6 (Leader: NXP)

WP6: Package/System Modeling and Design Exploration under Ambient Influence

  • T6.1: Thermal description of the system package and ambient influence

Heat diffusion is a phenomenon where the surrounding ambient has to be considered. This naturally includes the package, as well as the influence from the outside ambient. To to analyze and describe the different thermal systems, measurements and simulations will be performed. The wide range of products of the partners, from discrete components to complex ICs, ensures a good coverage of many applications currently in the market. The thermal characterization will be conducted under different ambient influences and the results will be used as input for modeling the effects of heating.

  • T6.2: Thermal distribution in 3D SiP stacks and 2D SoCs

While Task T6.1 is focussing on the macroscopic influencing factors as the package structure, this task focuses on describing the local impact of die temperature distribution due to self heating, and the description of thermal feedback.

  • T6.3: System-level thermal aware design

In this task, thermal design space exploration and automated thermal-aware design capabilities are developed.

wp7 leader nxp
WP7 (Leader: NXP)

WP7: Validation, Demonstration and Evaluation

  • T7.1: Validation of models on test structuresIn this task, models developed in other work-packages are validated on multiple test-structures at different levels of abstraction.

T7.2: Demonstration of design techniques on test chip

In this task, the new design techniques are validated on silicon test structures and test chips.

T7.3: Evaluation of prototype tools on test casesIn this task, prototype tools are evaluated on the test cases defined in Task T1.3, as well as on additional design examples provided by the industrial partners

wp8 leader st
WP8 (Leader: ST)

WP8: Dissemination, Training, Exploitation, Roadmapping

  • T8.1: Set-up and maintenance of the project web-site

The objective of this Task is the set-up and maintenance of a public web-site that will constitute the main point of collection of the project information, including public deliverables, summary of major scientific achievements advertisement of dissemination and training activities. Maintenance and incremental updates will take place monthly, major revisions and restructuring will occur every six months.

  • T8.2: Dissemination

The partners of the THERMINATOR Consortium will disseminate the project results through various means. This tasks covers all the dissemination activities.

  • T8.3: Training

The activities in this task are of two kinds. First, preparation of course material on thermal-aware design. Second, planning, advertisement, organization and execution of the courses. In the first year of the project, existing knowledge and new ideas from all partners will be collected and training material (in electronic form) will be generated by the participants of this task.

  • T8.4: Exploitation and Roadmapping

The partners of the THERMINATOR Consortium will exploitation the project results through various means. This tasks covers all the dissemination activities.