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Microcontroller 8051

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  1. In The Name Of God Microcontroller 8051 SUPARDI

  2. Contents: • Introduction • Block Diagram and Pin Description of the 8051 • Registers • Some Simple Instructions • Structure of Assembly language and Running an 8051 program • Memory mapping in 8051 • 8051 Flag bits and the PSW register • Addressing Modes • 16-bit, BCD and Signed Arithmetic in 8051 • Stack in the 8051 • LOOP and JUMP Instructions • CALL Instructions • I/O Port Programming SUPARDI

  3. Introduction General-purpose microprocessor • CPU for Computers • No RAM, ROM, I/O on CPU chip itself • Example:Intel’s x86, Motorola’s 680x0 Many chips on mother’s board Data Bus CPU General-Purpose Micro-processor Serial COM Port I/O Port RAM ROM Timer Address Bus General-Purpose Microprocessor System SUPARDI

  4. Microcontroller : • A smaller computer • On-chip RAM, ROM, I/O ports... • Example:Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X CPU RAM ROM A single chip Serial COM Port I/O Port Timer Microcontroller SUPARDI

  5. Microprocessor vs. Microcontroller Microprocessor • CPU is stand-alone, RAM, ROM, I/O, timer are separate • designer can decide on the amount of ROM, RAM and I/O ports. • expansive • versatility • general-purpose • Microcontroller • CPU, RAM, ROM, I/O and timer are all on a single chip • fix amount of on-chip ROM, RAM, I/O ports • for applications in which cost, power and space are critical • single-purpose SUPARDI

  6. Embedded System • Embedded system means the processor is embeddedinto that application. • An embedded product uses a microprocessor or microcontroller to do one task only. • In an embedded system, there is only one application software that is typically burned into ROM. • Example:printer, keyboard, video game player SUPARDI

  7. Three criteria in Choosing a Microcontroller • meeting the computing needs of the task efficiently and cost effectively • speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption • easy to upgrade • cost per unit • availability of software development tools • assemblers, debuggers, C compilers, emulator, simulator, technical support • wide availability and reliable sources of the microcontrollers. SUPARDI

  8. Block Diagram External interrupts On-chip ROM for program code Timer/Counter Interrupt Control Timer 1 On-chip RAM Counter Inputs Timer 0 CPU Serial Port Bus Control 4 I/O Ports OSC P0 P1 P2 P3 TxD RxD Address/Data SUPARDI

  9. Comparison of the 8051 Family Members Feature8051 8052 8031 ROM (program space in bytes) 4K 8K 0K RAM (bytes) 128 256 128 Timers 2 3 2 I/O pins 32 32 32 Serial port 1 1 1 Interrupt sources 6 8 6 SUPARDI

  10. SUPARDI

  11. Vcc P1.0 1 40 P0.0(AD0) P1.1 2 39 P0.1(AD1) P1.2 3 38 P0.2(AD2) P1.3 4 37 8051 (8031) P0.3(AD3) P1.4 5 36 P0.4(AD4) P1.5 6 35 P0.5(AD5) P1.6 7 34 P0.6(AD6) P1.7 8 33 P0.7(AD7) RST 9 32 (RXD)P3.0 EA/VPP 10 31 (TXD)P3.1 ALE/PROG 11 30 PSEN (INT0)P3.2 12 29 P2.7(A15) 13 28 (INT1)P3.3 (T0)P3.4 P2.6(A14) 14 27 (T1)P3.5 P2.5(A13) 15 26 P2.4(A12) (WR)P3.6 16 25 P2.3(A11) (RD)P3.7 17 24 P2.2(A10) XTAL2 18 23 P2.1(A9) XTAL1 19 22 P2.0(A8) GND 20 21 Pin Description of the 8051 PDIP/Cerdip  SUPARDI

  12. Pins of 8051(1/4) • Vcc(pin 40): • Vcc provides supply voltage to the chip. • The voltage source is +5V. • GND(pin 20):ground • XTAL1 and XTAL2(pins 19,18): • These 2 pins provide external clock. • Way 1:using a quartz crystal oscillator  • Way 2:using a TTL oscillator  • Example 4-1 shows the relationship between XTAL and the machine cycle.  SUPARDI

  13. Pins of 8051(2/4) • RST(pin 9):reset • It is an input pin and is active high(normally low). • The high pulse must be high at least 2 machine cycles. • It is a power-on reset. • Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. • Reset values of some 8051 registers  • Way 1:Power-on reset circuit  • Way 2:Power-on reset with debounce  SUPARDI

  14. Pins of 8051(3/4) • /EA(pin 31):external access • There is no on-chip ROM in 8031 and 8032 . • The /EA pin is connected to GND to indicate the code is stored externally. • /PSEN & ALE are used for external ROM. • For 8051, /EA pin is connected to Vcc. • “/” means active low. • /PSEN(pin 29):program store enable • This is an output pin and is connected to the OE pin of the ROM. • See Chapter 14. SUPARDI

  15. Pins of 8051(4/4) • ALE(pin 30):address latch enable • It is an output pin and is active high. • 8051 port 0 provides both address and data. • The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. • I/O port pins • The four ports P0, P1, P2, and P3. • Each port uses 8 pins. • All I/O pins are bi-directional. SUPARDI

  16. Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND Figure 4-2 (a). XTAL Connection to 8051  SUPARDI

  17. Using a TTL oscillator XTAL2 is unconnected. XTAL2 NC EXTERNAL OSCILLATOR SIGNAL XTAL1 GND Figure 4-2 (b). XTAL Connection to an External Clock Source  SUPARDI

  18. Example : Find the machine cycle for (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz. Solution: (a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 s (b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 s  SUPARDI

  19. RESET Value of Some 8051 Registers: Register Reset Value PC 0000 ACC 0000 B 0000 PSW 0000 SP 0007 DPTR 0000 RAM are all zero.  SUPARDI

  20. Figure 4-3 (a). Power-On RESET Circuit Vcc + 10 uF 31 EA/VPP X1 30 pF 19 11.0592 MHz 8.2 K X2 18 30 pF RST 9  SUPARDI

  21. Figure 4-3 (b). Power-On RESET with Debounce Vcc 31 EA/VPP X1 10 uF 30 pF X2 RST 9 8.2 K  SUPARDI

  22. Pins of I/O Port • The 8051 has four I/O ports • Port 0 (pins 32-39):P0(P0.0~P0.7) • Port 1(pins 1-8):P1(P1.0~P1.7) • Port 2(pins 21-28):P2(P2.0~P2.7) • Port 3(pins 10-17):P3(P3.0~P3.7) • Each port has 8 pins. • Named P0.X (X=0,1,...,7), P1.X, P2.X, P3.X • Ex:P0.0 is the bit 0(LSB)of P0 • Ex:P0.7 is the bit 7(MSB)of P0 • These 8 bits form a byte. • Each port can be used as input or output (bi-direction).  SUPARDI

  23. A B R0 DPTR DPH DPL R1 R2 PC PC R3 Some 8051 16-bit Register R4 R5 R6 R7 Some 8-bitt Registers of the 8051 Registers SUPARDI

  24. Some Simple Instructions MOV dest,source ; dest = source MOV A,#72H ;A=72H MOV A, #’r’ ;A=‘r’ OR 72H MOV R4,#62H ;R4=62H MOV B,0F9H ;B=the content of F9’th byte of RAM MOV DPTR,#7634H MOV DPL,#34H MOV DPH,#76H MOV P1,A ;mov A to port 1 Note 1: MOV A,#72H ≠ MOV A,72H After instruction “MOV A,72H ” the content of 72’th byte of RAM will replace in Accumulator. 80868051 MOV AL,72H MOV A,#72H MOV AL,’r’ MOV A,#’r’ MOV BX,72H MOV AL,[BX] MOV A,72H Note 2: MOV A,R3 ≡ MOV A,3 SUPARDI

  25. ADD A, Source ;A=A+SOURCE ADD A,#6 ;A=A+6 ADD A,R6 ;A=A+R6 ADD A,6 ;A=A+[6] or A=A+R6 ADD A,0F3H ;A=A+[0F3H] SUPARDI

  26. SETB bit ; bit=1 CLR bit ; bit=0 SETB C ; CY=1 SETB P0.0 ;bit 0 from port 0 =1 SETB P3.7 ;bit 7 from port 3 =1 SETB ACC.2 ;bit 2 from ACCUMULATOR =1 SETB 05 ;set high D5 of RAM loc. 20h Note: CLR instruction is as same as SETB i.e: CLR C ;CY=0 But following instruction is only for CLR: CLR A ;A=0 • Bit Addressable Page 359,360 SUPARDI

  27. SUBB A,source ;A=A-source-CY SETB C ;CY=1 SUBB A,R5 ;A=A-R5-1 ADC A,source ;A=A+source+CY SETB C ;CY=1 ADC A,R5 ;A=A+R5+1 SUPARDI

  28. DEC byte ;byte=byte-1 INC byte ;byte=byte+1 INC R7 DEC A DEC 40H ; [40]=[40]-1 CPL A ;1’s complement Example: MOV A,#55H ;A=01010101 B L01: CPL A MOV P1,A ACALL DELAY SJMP L01 NOP & RET & RETI All are like 8086 instructions.  CALL SUPARDI

  29. ANL - ORL - XRL EXAMPLE: MOV R5,#89H ANL R5,#08H RR – RL – RRC – RLC A EXAMPLE: RR A SUPARDI

  30. EDITOR PROGRAM Myfile.asm ASSEMBLER PROGRAM Myfile.lst Other obj file Myfile.obj LINKER PROGRAM Myfile.abs OH PROGRAM Myfile.hex Structure of Assembly language and Running an 8051 program ORG 0H MOV R5,#25H MOV R7,#34H MOV A,#0 ADD A,R5 ADD A,#12H HERE: SJMP HERE END SUPARDI

  31. ROM memory map in 8051 family 0000H 0000H 0000H 0FFFH 1FFFH 8751 AT89C51 8752 AT89C52 7FFFH Memory mapping in 8051 4k 8k 32k DS5000-32 from Atmel Corporation from Dallas Semiconductor SUPARDI

  32. 7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH Register Bank 3 18H 17H Register Bank 2 10H 0FH (Stack) Register Bank 1 08H 07H Register Bank 0 00H • RAM memory space allocation in the 8051 SUPARDI

  33. CY AC F0 RS1 RS0 OV -- P CY PSW.7 Carry flag AC PSW.6 Auxiliary carry flag -- PSW.5 Available to the user for general purpose RS1 PSW.4 Register Bank selector bit 1 RS0 PSW.3 Register Bank selector bit 0 OV PSW.2 Overflow flag -- PSW.1 User define bit P PSW.0 Parity flag Set/Reset odd/even parity RS1 RS0 Register Bank Address 0 0 0 00H-07H 0 1 1 08H-0FH 1 0 2 10H-17H 1 1 3 18H-1FH 8051 Flag bits and the PSW register • PSW Register SUPARDI

  34. Instructions that Affect Flag Bits: Note: X can be 0 or 1 SUPARDI

  35. Example: MOV A,#88H ADD A,#93H 88 10001000 +93 +10010011 ---- -------------- 11B 00011011 CY=1 AC=0 P=0 Example: MOV A,#38H ADD A,#2FH 38 00111000 +2F +00101111 ---- -------------- 6701100111 CY=0 AC=1 P=1 Example: MOV A,#9CH ADD A,#64H 9C10011100 +64 +01100100 ---- -------------- 100 00000000 CY=1 AC=1 P=0 SUPARDI

  36. Addressing Modes • Immediate • Register • Direct • Register Indirect • Indexed SUPARDI

  37. Immediate Addressing Mode MOV A,#65H MOV A,#’A’ MOV R6,#65H MOV DPTR,#2343H MOV P1,#65H Example : Num EQU 30 … MOV R0,Num MOV DPTR,#data1 … ORG 100H data1: db “IRAN” SUPARDI

  38. Register Addressing Mode MOV Rn, A ;n=0,..,7 ADD A, Rn MOV DPL, R6 MOV DPTR, A MOV Rm, Rn SUPARDI

  39. Direct Addressing Mode Although the entire of 128 bytes of RAM can be accessed using direct addressing mode, it is most often used to access RAM loc. 30 – 7FH. MOV R0, 40H MOV 56H,A MOV A, 4 ; ≡ MOV A, R4 MOV 6, 2 ; copy R2 to R6 ; MOV R6,R2 is invalid ! SFR register and their address MOV 0E0H, #66H ; ≡ MOV A,#66H MOV 0F0H, R2 ; ≡ MOV B, R2 MOV 80H,A ; ≡ MOV P1,A • Bit Addressable Page 359,360 SUPARDI

  40. Register Indirect Addressing Mode • In this mode, register is used as a pointer to the data. MOV A,@Ri ; move content of RAM loc.Where address is held by Ri into A ( i=0 or 1 ) MOV @R1,B In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB insructions. Example: Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM location starting at 59h. Solution: MOV R0,37h ; source pointer MOV R1,59h ; dest pointer MOV R2,10 ; counter L1: MOV A,@R0 MOV @R1,A INC R0 INC R1 DJNZ R2,L1 • jump SUPARDI

  41. Indexed Addressing Mode And On-Chip ROM Access • This mode is widely used in accessing data elements of look-up table entries located in the program (code) space ROM at the 8051 MOVC A,@A+DPTR A= content of address A +DPTR from ROM Note: Because the data elements are stored in the program (code ) space ROM of the 8051, it uses the instruction MOVC instead of MOV. The “C” means code. SUPARDI

  42. Example: Assuming that ROM space starting at 250h contains “Hello.”, write a program to transfer the bytes into RAM locations starting at 40h. Solution: ORG 0 MOV DPTR,#MYDATA MOV R0,#40H L1: CLR A MOVC A,@A+DPTR JZ L2 MOV @R0,A INC DPTR INC R0 SJMP L1 L2: SJMP L2 ;------------------------------------- ORG 250H MYDATA: DB “Hello”,0 END Notice the NULL character ,0, as end of string and how we use the JZ instruction to detect that. SUPARDI

  43. Example: Write a program to get the x value from P1 and send x2 to P2, continuously . Solution: ORG 0 MOV DPTR, #TAB1 MOV A,#0FFH MOV P1,A L01: MOV A,P1 MOVC A,@A+DPTR MOV P2,A SJMP L01 ;---------------------------------------------------- ORG 300H TAB1: DB 0,1,4,9,16,25,36,49,64,81 END SUPARDI

  44. 16-bit, BCD and Signed Arithmetic in 8051 Exercise: • Write a program to add n 16-bit number. Get n from port 1. And sent Sum to LCD a) in hex b) in decimal • Write a program to subtract P1 from P0 and send result to LCD • (Assume that “ACAL DISP” display A to LCD ) SUPARDI

  45. MUL & DIV • MUL AB ;B|A = A*B MOV A,#25H MOV B,#65H MUL AB ;25H*65H=0E99 ;B=0EH, A=99H • MUL AB ;A = A/B, B = A mod B MOV A,#25 MOV B,#10 MUL AB ;A=2, B=5 SUPARDI

  46. 7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH Register Bank 3 18H 17H Register Bank 2 10H 0FH (Stack) Register Bank 1 08H 07H Register Bank 0 00H Stack in the 8051 • The register used to access the stack is called SP (stack pointer) register. • The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07. SUPARDI

  47. 0BH 0BH 0BH 0BH F3 25 12 25 12 25 0AH 0AH 0AH 0AH 09H 09H 09H 09H 08H 08H 08H 08H SP=09H SP=08H Start SP=07H SP=08H Example: MOV R6,#25H MOV R1,#12H MOV R4,#0F3H PUSH 6 PUSH 1 PUSH 4 SUPARDI

  48. LOOP and JUMP Instructions • DJNZ: Write a program toclear ACC, then add 3 to the accumulator ten time Solution: MOV A,#0; MOV R2,#10 AGAIN: ADD A,#03 DJNZ R2,AGAING ;repeat until R2=0 (10 times) MOV R5,A SUPARDI

  49. Other conditional jumps: SUPARDI

  50. SJMP and LJMP: LJMP(long jump) LJMP is an unconditional jump. It is a 3-byte instruction in which the first byte is the opcode, and the second and third bytes represent the 16-bit address of the target location. The 20byte target address allows a jump to any memory location from 0000 to FFFFH. SJMP(short jump) In this 2-byte instruction. The first byte is the opcode and the second byte is the relative address of the target location. The relative address range of 00-FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the current PC. SUPARDI