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Timing Analysis in Quartus. Features. Quartus is capable of doing single clock design timing analysis and multi-clock design timing analysis Single clock timing analysis Fmax (maximum clocking frequency) Tsu, Th, Tco (setup time, hold time, clock-to-out time)

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features
Features
  • Quartus is capable of doing single clock design timing analysis and multi-clock design timing analysis
  • Single clock timing analysis
    • Fmax (maximum clocking frequency)
    • Tsu, Th, Tco (setup time, hold time, clock-to-out time)
    • Slack analysis for Fmax (incl. delays to/from pins)
  • Multi-clock analysis
    • Allows user to analyze timing for a design containing register-to-register paths which are controlled by different clocks
    • Slack analysis is used
  • Combinatorial Loop Detection
    • Quartus automatically detects combinatorial loops
features1
Features
  • Different types of timing information (Refer to the compilation section for more information)
    • Timing without place & route
    • Timing with place & route
    • A mix of both for a hierarchical design
  • By default, timing analysis is performed automatically after compilation
    • Can be disabled
  • Timing information can be exported to other EDA tools via VHDL, Verilog and Standard Delay File (SDF)
in this section
In This Section
  • Timing analysis for a single clock system
    • Register Performance
    • Setup Time
    • Hold Time
    • Clock-to-Out
  • Making Timing Assignments
  • Timing analysis of a multi-clock system
  • How to make multi-cycle assignments
  • Timing Wizard
compile design
Compile Design

Step 1:

The internal fmax is 83.19 Mhz. This value is automatically given for each clock in the Message Window (Processing Tab)

Step 2:

Investigate the type of delay

in this design

reporting timing results
Reporting Timing Results
  • Timing information is part of the Compilation Report
    • Summary

Timing Analyses

    • fmax (not incl. delays to/from pins) or

fmax (incl. delays to/from pins)

    • Register-to-Register Table
    • tsu (Input Setup Times)
    • th (Input Hold Times)
    • tco (Clock to Out Delays)
    • tpd (Pin to Pin Delays)
  • All timing results are reported here
fmax not incl delays to from pins
fmax (not incl. delays to/from pins)

tco

B

tsu

C

E

Clock Period

Clock Period = Clock-to-out + Data Delay + Setup Time - Clock Skew

= tco + B + tsu - (E - C)

Fmax = 1/Clock Period

fmax analysis
fmax Analysis

fmax values are listed in ascending order. The worst fmax is listed on the top.

Quartus Detected Clock

Select fmax

Destination Register

Worst fmax

fmax analysis1
fmax Analysis
  • Timing Analysis By Default Lists 10 Worst Paths
    • Can Change in Project -> Timing Settings (discussed later)

Source registers and associated fmax values

Expand to see the source registers feeding the selected destination register

fmax analysis2
fmax Analysis
  • To Analyze the Path More Closely

Highlight & right mouse and select List Paths

The steps above are similar for all timing path analysis in Quartus

fmax analysis3
fmax Analysis

Data Delay (B)

Destination Register Clock Delay (E)

Source Register Clock Delay (C)

Clock to Output (tco)

Setup Time (tsu)

Messages Window (System Tab) in Quartus

B

tco

tsu

C

E

1

= 83.08 MHz

0.33 ns + 11.257 ns + 0.45 ns + 0.00

Clock Period

fmax analysis4
fmax Analysis

This signal path consists of 11 locations

Destination Cell

Interconnect Delay

Cell Delay

Running Total

The convention above is similar for all timing path analysis in Quartus

carry chain in data delay path
Carry Chain in Data Delay Path

Floorplan:

Logic Cell View

Note:

If the delay path involves a carry chain, you can only see the delay path value in the Floorplan when the Floorplan is set to Logic Cell View. LAB View does not show that delay path.

0.191ns is equal

to the carry chain delay

plus combinatorial delay

0.000 ns + 0.191 ns = 0.191 ns

0.000 ns is the carry chain delay (interconnect delay)

0.191 ns is the combinatorial delay

locate delay path in floorplan
Locate Delay Path in Floorplan

Highlight path

Right click & select Locate

The steps above are similar for all timing path analysis in Quartus

locate delay path in floorplan1
Locate Delay Path in Floorplan

11.257 ns is the

total register to register delay path

fmax incl delays to from pins
Fmax (incl. delays to/from pins)

A

B

tco

tsu

Q

C

External

Input Delay

External

Output Delay

E

Input Pin Period

Clock Period

Out Pin Period

System Fmax = 1 / (the longest of the 3 following delays:

Clock Period, Input Pin Period, Output Pin Period)

Clock Period = C + tco + B - E + tsu

Input Pin Period = External Input Delay + A - C + tsu

Output Pin Period= E + tco + Q + External Output Delay

input pin period
Input Pin Period

A

tsu

C

External

Input Delay

Input Pin Period

Input Pin Period = External Input Delay + A - C + tsu

Value entered in Quartus (shown later)

external input delay
External Input Delay

External Input Delay

Altera Device

Imaginary Register

ET

A

tco

tsu

EC

C

External Input Delayis used to model the delay between an imaginary register and a register inside an Altera device

External Input Delay= EC + tco + ET

Input Pin Period = External Input Delay + A - C + tsu

output pin period
Output Pin Period

tco

Q

External

Output Delay

E

Output Pin Period

Output Pin Period = E + tco + Q + External Output Delay

Value entered in Quartus (shown later)

external output delay
External Output Delay

Altera Device

External Output Delay

Imaginary Register

Q

ET

dst

tco

tsu

E

EC

External Output Delayis used to model the delay between a registered output from an Altera device to an imaginary register

External Output Delay= ET + tsu - EC

Output Pin Period = E + tco + Q + External Output Delay

fmax incl delays to from pins1
Fmax (incl. delays to/from pins)

The worst fmax is shown at the top by default.

Select fmax (incl. Delays to/from pins)

Fmax values

External Delay is shown in Messages Window after List Path

setting external input output delay
Setting External Input/Output Delay
  • Default (Global) External Delay for all I/Os

1)Project -> Timing Settings

2)Select Default External

Delays

3)Set Delay Value(s)

setting external input output delay1
Setting External Input/Output Delay
  • Individual Pin(s)

1)Tools -> Assignment Organizer

2)Locate Pin(s)

3)Select Timing from Assignment Categories

3)Set Delay Value(s)

for Pin(s)

setup time analysis
Setup Time Analysis

Data delay

intrinsic tsu

tsu

Clock delay

tsu = data delay - clock delay + intrinsic tsu

setup time analysis1
Setup Time Analysis

The greatest setup time is shown at the top by default.

Input Pin Name

Clock Name

Select tsu

All Registers Fed by Pin

thold analysis
thold Analysis

Data delay

intrinsic thold

thold

Clock delay

thold = clock delay - data delay + intrinsic thold

thold analysis1
thold Analysis

The longest hold time is shown at the top by default.

Input Pin (Data) Name

Register Name

Select th

Clock Name

Negative hold times are shown as “<= 0”

tco analysis
tco Analysis

intrinsic tco

Data delay

tco

Clock delay

clock delay + intrinsic tco + data delay = tco

tco analysis1
tco Analysis

The slowest clock-to-output time is shown at the top by default.

Output Pin Name

Clock Name

Select tco

Register Name

timing analysis options
Timing Analysis Options
  • Used to Limit Which Paths Are Displayed by Timing Analyzer
  • Two Ways to Set Options
    • Project -> Timing Settings -> Other Requirements & Options
    • Project -> Timing Wizard
  • Examples
    • Cut Off Feedback From I/O Pins (next slide)
    • Cut Off Clear and Preset Signal Paths
      • If checked, Quartus Will Not Analyze Register Clear and Preset Delays
    • Cut Off Read During Write Signal Paths
      • Turn ON if Read During Write is an Invalid Path
option cut off feedback from i o pin
Option: Cut Off Feedback from I/O Pin

Global Timing Option: Cut off feedback from I/O Pin

  • Used to break I/O pin from the analysis
  • When on, paths A and B are valid. C is not valid.
  • When off, paths A, B, and C are valid.

I/O Pin

Register 2

Register 1

B

A

Q

D

C

clk

timing analysis options2
Timing Analysis Options
  • Used to Limit How Many Paths Are Displayed by Timing Analyzer
  • How to Set Option
    • Project -> Timing Settings -> Timing Analysis Reporting
  • Examples
    • Show “XX” Source Nodes Per Destination Node
      • Controls by Number How Many Paths Are Displayed
    • Exclude Paths With fmax Greater Than “XX”
      • Controls by Parameter Value (fmax) How Many Paths Are Displayed
    • Exclude Paths For tsu, tco, thd Also
timing analysis options3
Timing Analysis Options

List 10 Paths

List Paths with fmax less than 50 MHz

List Paths with tsu greater than 3 ns

single clock timing analysis
Single Clock Timing Analysis
  • The timing analysis that we just went over can be classified as a single clock frequency analysis
  • Single clock frequency analysis is automatically done during each compile
  • Quartus will automatically detect clocks if no assignments are made
    • More information about clock assignments is coming up in multi-clock timing analysis
  • Check results in Report Window
timing assignments
Timing Assignments
  • Timing assignments have two impacts on designs
    • 1. During timing analysis, they specify required times the design is measured against
    • 2. During compilation, they become timing requirements which Quartus has to meet when performing timing driven compilation (TDC)
      • Note: by default, TDC is on
  • 5 types of timing assignments exist:
    • fmax, tsu, thold, tco, tpd
  • These timing assignments can be assigned globally or locally
examples of timing assignments
Examples of Timing Assignments

Timing Assignments used in Timing Analysis

fmax timing assignment

The values are BLACK, because Actual fmax meets the Required fmax

tsu timing assignment. The numbers are RED, because the Actual tsu does not meet the Required tsu

timing driven compilation
Timing Driven Compilation
  • Timing Driven Compilation (TDC) directs the compiler to synthesize and place logic to meet timing specified requirements
    • Critical paths will be placed closer together in the device

Optimize for I/O Timing and/or Internal Timing

Choose

Normal or

Extra Effort

(works harder &

takes longer)

global assignment timing settings
Global Assignment: Timing Settings

Global Clock Assignment for a single clock design

For a design with separate clocks, you can enter the required fmax. The Default required fmax will be applied to each individual clock in the design.

global assignments timing settings
Global Assignments - Timing Settings

Global tsu. All input or bidirectional pins are measured against this tsu requirement

Global th. All input or bidirectional pins are measured against this th requirement

Global tco. All registers driving outputs or bidirectional pins are measured against this tco requirement

Global tpd. All pin-to-pin delays are measured against this tpd requirement

individual assignments
Individual Assignments
  • tsu (setup time) and th (hold time) assignments
    • Single point assignment
    • Point-to-point assignment
  • tco (clock-to-out) assignment
    • Single point assignment
    • Point-to-point assignment
timing assignments1
Timing Assignments
  • What can be tagged with a timing assignments?
    • Registers (all)
    • Clock Pins (all)
    • Input Pins (tsu, th)
    • Output Pins (tco)
    • Bidirectional Pins (all)
setup hold requirements
Setup/Hold Requirements
  • Assignments can be either single point or point-to-point
  • Single point setup/hold requirements
    • States that the setup/hold time is required on every register that the pin feeds

Assign single point setup/hold requirement to the data pin

setup hold requirement point to point
Setup/Hold Requirement: Point-to-Point
  • The setup/hold time is required only for the specified path

Assign point-to-point setup requirement to the input pin and the destination register

Reg1

data0

Reg2

clock to out requirements
Clock To Out Requirements

...

...

  • Either a single point or a point-to-point assignment
  • Same idea as setup/hold time requirements
  • Tco requirement on a clock pin
    • Means that all Tco paths that start from the specified clock must meet this requirement
clock to out requirements1
Clock To Out Requirements
  • tco requirement on an output pin
    • Means that all paths from clocks to the specified output pin must meet this requirement
clock to out requirements2
Clock To Out Requirements
  • Point-to-point tco requirement
    • Can specify that all paths that go from a specific clock pin to a specific output pin must meet this requirement
example assign setup requirement
Example: Assign Setup Requirement

Step 1: Enter the data pin name or use the Node Finder to locate data pin name and/or register name

Menu Bar: Tools > Assignment Organizer...

Step 2: Select Timing from the Assignment Category box

Step 3: Choose tsu Requirement from the drop-down list in the Settings section

example assign setup requirement1
Example: Assign Setup Requirement

Step 6: Click Add to add the assignment

Step 4: Type in the setup requirement

Step 5: Use Fed by: to create a point-to-point requirement

multi clock frequency analysis
Multi-Clock Frequency Analysis
  • Allows user to analyze timing for a design containing register-to-register paths which are controlled by different clocks
    • Unless Specified, Quartus Treats Individual Clocks As Having the Same Frequency and Phase

Combinatorial logic

Register 2

Register 1

data

tsu

tco

clk2

clk1

launching edge

clk1

clk2

capturing edge

slack between two clock domains
Slack Between Two Clock Domains
  • Slack is used to keep track of the delay between Register 1 and Register 2

Positive Slack

    • If the slack is positive, then the data from Register 1 will meet the setup time of Register 2

Negative Slack

    • If the slack is negative, then the data from Register 1 will violate the setup time of Register 2

Combinatorial logic

Register 2

Register 1

data

tsu

tco

clk2

clk1

equation for slack
Equation for Slack

Slack = Required Time - Actual Time

Slack = Slack Clock Period - ( Intrinsic tco + Data Delay + Intrinsic tsu )

Slack clock period

launching edge

clk1

capturing edge

clk2

Combinatorial logic

Register 2

Register 1

data

tsu

tco

clk2

clk1

data delay

calculating slack in quartus
Calculating Slack in Quartus
  • In order for Quartus to calculate the Slack between registers, timing assignments need to be entered by the user
  • IMPORTANT: The slack section inside the compilation report file does not appear automatically for a multi-clock design
    • Timing assignments need to take place first
slack analysis steps to follow
Slack Analysis: Steps to Follow
  • Follow the steps below to prepare Quartus for Slack Analysis
    • Create Clock Settings
      • Define a base clock
      • Define other clock/s that is/are relative to the base clock
    • Assign Clock Settings to actual clocks
    • Recompile design
    • Look at result in the slack timing table
create clock settings
Create Clock Settings
  • Minimum of 2 clock settings exist for a multi-clock design:
    • One is a base clock
    • Second is a derived clock referenced to a “base” clock
      • Derived clocks can be any ratio (m/d) of base clock plus an added offset, if desired.

Note: If the design has more than 2 clocks, additional derived or base clocks can be created

  • derived clock = base clock x (m/d) + offset

launching edge

base clock

derived clock

capturing edge

offset

create clock setting base clock
Create Clock Setting: Base Clock

Menu Bar: Project > Timing Settings...

Step 1: Click New to Add New Setting

create clock setting base clock1
Create Clock Setting: Base Clock

Menu Bar: Project > Timing Settings...

Step 2: Enter the name of the clock setting

Step 3: Select Independent of other clock settings

Step 4: Adjust fmax and Duty Cycle

Step 5: Click OK to Add Setting

create clock setting derived clock
Create Clock Setting: Derived Clock

Menu Bar: Project > Timing Settings...

Step 1: Click New to Add a New Setting

create clock setting derived clock1
Create Clock Setting: Derived Clock

Menu Bar: Project > Timing Settings...

Step 2: Enter the Name of the Derived Clock Setting

Step 3: Select clock setting that this derived clock is based on

Step 4: Click on Derived Clock Requirements

create clock setting derived clock2
Create Clock Setting: Derived Clock

Step 5: Adjust ratio and offset. The derived clock duty cycle is not affected by the multiply base or the divide base. Invert base clock is also available. Click OK when done.

Step 6: Click OK to Add Setting

current clock settings
Current Clock Settings
  • At this point, an absolute clock setting called base clock and a derived clock setting called derived clock have been created. The next step is to apply these clock settings to the actual clock nets.

Absolute clock setting

called base

Derived clock setting

called derived

slack analysis steps to follow1
Slack Analysis: Steps to Follow
  • Follow the steps below to prepare Quartus for Slack Analysis
    • Create Clock Settings
      • Define a base clock
      • Define other clock/s that is/are relative to the base clock
    • Assign Clock Settings to actual clocks
    • Recompile design
    • Look at slack results in compilation report file
assign absolute clock settings to clock
Assign Absolute Clock Settings to Clock

Menu Bar: Tools > Assignment Organizer...

Step 1: Enter the name of the clock pin. The naming convention is: || of the pin>

or click on the Node Finder to select the clock pin

Step 2: Click on Timing and select Clock Setting

Step 3: Select Base Clock Settings for this specific clock pin. Click on Add

Derived Clock Setting:

Repeat Step 1 to Step 3 for the derived clock setting

slack analysis steps to follow2
Slack Analysis: Steps to Follow
  • Follow the steps below to prepare Quartus for Slack Analysis
    • Create Clock Settings
      • Define a base clock
      • Define other clock/s that is/are relative to the base clock
    • Assign Clock Settings to actual clocks
    • Recompile design
    • Look at slack results in compilation report file
recompile design view slack information
Recompile Design & View Slack Information

Recompile design

Slack

During compilation,

slack information is reported in the message window

slack distribution
Slack Distribution

Determine if any and/or how many

nodes receive a negative slack?

Select

IMPORTANT:Negative Slack Time

needs to be corrected in order

for the design to work

slack time table
Slack Time Table
  • Slack Time Table offers more details about the source nodes and destination nodes
    • Positive slack means the timing was met
    • Negative slack shows by how much the timing was not met
    • IMPORTANT: Design needs to be altered or multi-cycle timing requirement/s is/are needed to resolve the negative slack issues

Select

Negative slack times show up in red and are listed at the top of the table

slack analysis steps to follow3
Slack Analysis: Steps to Follow
  • Follow the steps below to prepare Quartus for Slack Analysis
    • Create Clock Settings
      • Define a base clock
      • Define other clock/s that is/are relative to the base clock
    • Assign Clock Settings to actual clocks
    • Recompile design
    • Look at slack results in compilation report file
multicycle paths
Multicycle Paths
  • Signal Paths That Intentionally Require More Than One Cycle to Become Stable
    • Must Be Considered in Design Implementation
  • Declaring a Multicycle Path Tells the Timing Analyzer to Account for Multiple Clock Edges Between Nodes or Clock Domains

launching edge

base clock

derived clock

capturing edge

assigning multicycle paths
Assigning Multicycle Paths
  • Destination Register
    • Multi-cycle assignment is applied to all signal paths feeding register
  • Register-to-Register
    • Point-to-point assignment that applies to one source register and one destination register
  • Two Clock Domains
    • Assignment applies to all signals that travel from one clock domain to another

launching edge

base clock

derived clock

capturing edge

comparable offset vs clock period
Comparable Offset vs. Clock Period
  • If the value of your offset is comparable to the value of the clock period, then a multi-cycle assignment on the derived clock is usually unnecessary.
    • ex. offset = 11ns, clock period = 20ns

launching edge

base clock

derived clock

capturing edge

offset

relatively small offset vs clock period
Relatively Small Offset vs. Clock Period

offset

  • If the offset value is relatively small compared to the clock period, then a multi-cycle assignment is usually necessary on the derived clock
    • Ex. Clock period = 10ns, offset = 2ns
    • The offset can be thought of as clock skew

launching edge

base clock

derived clock

Intended capturing edge

offset

However, by default, Quartus assumes this is the capturing edge

inverted clock
Inverted Clock
  • If your design uses both the true and complement of the same clock signal, then a multi-cycle assignment is not necessary
    • You can assign the true clock as the base clock
    • You can assign the complement as the inverse of the base clock

launching edge

true clock

(base clock)

complement clock

(derived clock)

capturing edge

non integer multiples
Non-Integer Multiples
  • If the design clocks are non-integer multiples of each other, then a multi-cycle assignment may be necessary
    • Quartus analyzes two closest edges of base & derived clocks

These two edges are most likely to cause a setup violation of the destination register

base clock

(source)

derived clock

(destination)

Ex. base clock = derived clock * 3/4

non integer multiples1
Non-Integer Multiples
  • If the design clocks are non-integer multiples of each other, then a multi-cycle assignment may be necessary
    • Quartus analyzes two closest edges of base & derived clocks

launching edge

2

1

base clock

(source)

derived clock

(destination)

capturing edge

Ex. base clock = derived clock * 3/4

multi cycle assignment
Multi-Cycle Assignment

offset

  • Multi-cycle assignment on the derived clock indicates the capturing edge is not the closest rising edge.

2)The base clock is the reference clock for counting the number of edges between the capturing edge and launching edge

1)For multi-cycle assignments, the capturing edge is the reference edge

launching edge

2

1

base clock

derived clock

capturing edge

offset

Multi-cycle assignment indicates this is the capturing edge

making a multi cycle assignment
Making a Multi-Cycle Assignment

Menu Bar: Tools > Assignment Organizer...

1)Choose Timing and Multicycle from the Assignment List

2)Specify the number of edges

3)Use Fed by if creating two clock assignment or point-to-point

timing wizard
Timing Wizard
  • Easy way to enter timing assignments
  • Consolidates all timing assignments in one menu
    • Individual clock settings OR overall circuit frequency
    • Default system timing
      • tsu
      • th
      • tco
      • tpd
    • Default external input/output delays
    • Enable/Disable timing analysis

during compilation

    • Timing driven compilation
summary
Summary
  • Timing analysis for a single clock system
    • Registered Performance
    • Setup Time
    • Hold Time
    • Clock-to-Out
  • Making Timing Assignments
  • Multi-clock timing analysis
  • Multi-cycle timing assignments
  • Timing Wizard
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