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Multioperand Addition

This lecture covers multioperand addition, including inner product multiplication, serial implementation, and examples using ripple-carry and carry-save adders.

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Multioperand Addition

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  1. Lecture 6 Multioperand Addition

  2. Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 8, Multioperand Addition Note errata at: http://www.ece.ucsb.edu/~parhami/text_comp_arit_1ed.htm#errors

  3. Recommended Reading J-P. Deschamps, G. Bioul, G. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems Chapter 11.1.12 Multioperand Adders

  4. Applications of multioperand addition Inner product Multiplication n-1 n-1 p=a·x s =  x(i) y(i)=  p(i) i=0 i=0

  5. # of bits of S = log2 (Smax + 1) = = log2 (n (2k-1) + 1)  log2 n 2k = = k + log2 n Number of bits of the result n-1 S =  x(i) x(i) [0..2k-1] i=0 Smin = 0 Smax = n (2k-1)

  6. Serial implementation of multioperand addition

  7. Adding 7 numbers in the binary tree of adders

  8. Ripple-carry adders at levels i and i+1

  9. Example: Adding 8 3-bit numbers

  10. Ripple-Carry Carry Propagate Adder (CPA) a2 b2 a1 b1 a0 b0 an-1 bn-1 c0 c3 c2 c1 cn cn-1 . . . FA FA FA FA s2 s1 s0 sn-1

  11. Carry Save Adder (CSA) cn-1 c2 c1 c0 bn-1 b2 b1 b0 an-1 a2 a1 a0 . . . FA FA FA FA c3 c2 s2 s3 c1 s1 s0 sn-1 cn cn-1

  12. A Ripple-Carry vs. Carry-Save Adder

  13. Operation of a Carry Save Adder (CSA) Example 20 22 23 24 21 x y z 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 s c 0 0 1 1 0 1 1 011 x+y+z = s + c

  14. Carry propagate and carry-save adders in dot notation

  15. Specifying full- and half-adder blocks in dot notation

  16. x3 x2 x1 x0 y3 y2 y1 y0 z3 z2 z1 z0 w3 w2 w1 w0 s3 s2 s1 s0 c4 c3 c2 c1 w3 w2 w1 w0 c4 s3 s2 s1 s0 c4 c3 c2 c1 ’ ’ ’ ’ ’ ’ ’ ’ S5 S4 S3 S2 S1 S0 Carry-save adder for four operands

  17. Carry-save adder for four operands s0 s3 s2 c2 s1 c1 c3 c4 s0 ’ ’ s3 s2 s1 ’ ’ c4 ’ c3 c2 c1 ’ ’ ’

  18. Carry-save adder for four operands z y w x 4 4 4 4 CSA c s CSA s’ c’ CPA S

  19. Carry-save adder for six operands Implementation of one-bit slice CSA tree

  20. Tree of carry save adders reducing seven numbers to two

  21. Addition of seven six-bit numbers in dot notation

  22. Adding seven k-bit numbers: block diagram

  23. Relationship Between Number of Inputs and Tree Height

  24. Parameters of tree carry-save adders (1) Latency LatencyCSA = h(n)  TFA + LatencyCPA(k, n) Tree height for n operands Component Adders Widths typically close to k bits k .. k + log2 n CSA  k + log2 n CPA

  25. 3 3 3 2 2 2 Parameters of tree carry-save adders (2) Maximum number of inputs that can be reduced to two by an h-level tree, n(h) n(0) = 2 n(h) = n(h-1) n(1) = 3 n(2) = 4 n(3) = 6 n(4) = 9 n(5) = 13 n(6) = 19 2 ( )h-1 < n(h)  2 ()h

  26. Parameters of tree carry-save adders (3) Smallest height of the tree carry save adder for n operands, h(n) h(n) = 1 + h( ) 2 n 3 h(2) = 0 h(n)  log ( ) n 3 2 2

  27. Wallace vs. Dadda Trees (1) Wallace trees • Reduce the size of the final Carry Propagate Adder (CPA) • Optimum from the point of view of speed Dadda trees • Reduce the cost of the carry save tree • Optimum (among the CSA trees) from the point of • view of area

  28. Wallace vs. Dadda Trees (2) • Wallace reduces number of operands at earliest opportunity • Goal of this is to have smallest number of bits for CPA adder • However, sometimes having a few bits longer CPA adder does not affect the propagation delay significantly (i.e. carry-lookahead) • Dadda seeks to reduce the number of FA and HA units • May be at the cost of a slightly larger final CPA

  29. Wallace Tree

  30. Dadda Tree

  31. 5-to-3 Parallel Counter 22 23 21 20 24 a b c d e 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 s0 s1 s2 0 1 1 1 0 0 1 1 0 0 1 0 0 1 1 a+b+c+d+e = s0+s1+s2

  32. Implementation of 1-bit of 5-to-3 parallel counter using single CLB slice of a Virtex FPGA

  33. c d e a b w w w w w PC s1 s2 s0 CSA CPA w y=a+b+c+d+e mod 2w Carry Save Adder vs. 5-to-3 Parallel Counter a b c d e w w w w w CSA CSA CSA CPA w y=a+b+c+d+e mod 2w

  34. Fig. 8.17 Dot notation for a (5, 5; 4)-counter and the use of such counters for reducing five numbers to two numbers. Unequal columns Generalized Parallel Counters Multicolumn reduction (5, 5; 4)-counter Generalized parallel counter = Parallel compressor (2, 3; 3)-counter

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