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Machine Organization ( Part 3)

Machine Organization ( Part 3). CHAPTER 3. INSTRUCTION Cycle. Instruction Cycle. The microprocessor’s main task is to execute instructions. The instruction cycle is therefore at the heart of understanding the function and operation of the microprocessor.

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Machine Organization ( Part 3)

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  1. Machine Organization (Part 3) CHAPTER 3

  2. INSTRUCTION Cycle

  3. Instruction Cycle • The microprocessor’s main task is to execute instructions. • The instruction cycle is therefore at the heart of understanding the function and operation of the microprocessor. • The time begins when the address for retrieving an instruction from memory is placed on the address bus for a fetch, and ending when the execution phase is completed.

  4. Instruction Cycle • Fetch cycle • Find and Decode instruction, load from memory into register and signal the ALU • Execute cycle. • Performs operation that instruction requires • Move/transform data

  5. Instruction Cycle • Generally, a microprocessor carries out instructions in a three-step (or phase) process. • It simply repeats the three-step operation with almost no variation, as long as power is applied to it. • These three steps are called • Fetch • Decode • Execute

  6. Instruction Cycle – Phase 1: Fetch • Fetching, in a microprocessor, is the term used to indicate that the microprocessor is retrieving an instruction from memory. • The microprocessor fetches the instructions from memory one at a time, and brings them into the instruction decoder register to be decoded.

  7. Instruction Cycle – Phase 2: Decode • The decode phase of the cycle begins as soon as the instruction, in the form of an 8-bit byte, appears in the instruction decoder register. • The decoding is done via PLA (Programmable Logic Array). The array will output the control signals necessary to carry out the instruction. • The PLA is designed with microcode to recognize only those bit patterns contained in the instruction set. Upon recognition of a bit pattern the PLA or microcode then generates the internal and external control signals necessary to carry out the given instruction. • Microcode is a layer of hardware-level instructions or data structures involved in the implementation of higher level machine code instructions in central processing units.Microcode resides in special high-speed memory (ROM) and translates machine instructions into sequences of detailed circuit-level operations

  8. Instruction Cycle - Phase 3: Execute • The execution phase begins as soon as the microcode outputs the control signal necessary to carry out the instruction. • The length of time needed to complete the execution phase varies considerably with the type of instruction involved. • Some instructions are several bytes long. • Each byte is fetched and decoded one at a time. • After each byte is decoded, the necessary control signals are executed.

  9. Fetch-Execute Instruction Cycle • Basis for every capability of a computer • Ultimately the operation of a computer as a whole is defined by the primary operations that can be performed with registers • to move data between registers • to add or subtract data to a register • to shift data within a register • to test the value in a register for certain conditions such as negative, positive or zero.

  10. Fetch-Execute Instruction Cycle • Basically, the registers involved are: 1. General purpose (GP) registers or accumulator (A) :  used to hold data values between instructions 2. Program counter (PC) :  hold the address of the current instruction 3. Instruction register (IR) :  hold the current instruction while it is being executed 4. Memory address register and memory data register (MAR & MDR) :  used for accessing memory

  11. Fetch-Execute Instruction Cycle • To execute an instruction, 2 phases involve : • Fetched the instruction from memory • address of the current instruction to be executed identified by the value in PC register • this value transferred into MAR so that the computer can retrieve the instruction located at that address STEP 1 : PC  MAR • this will result in the instruction being transferred from the specified memory location to MDR • that instruction is transferred to IR STEP 2 : MDR  IR

  12. Instruction Cycle – Fetch Cycle

  13. Instruction Cycle – Execute Cycle • This cycle is instruction dependent. The instructions can be categorized into the following four groups: • CPU - Memory: Data may be transferred from memory to the CPU or from the CPU to memory. • CPU - I/O: Data may be transferred from an I/O module to the CPU or from the CPU to an I/O module.

  14. Instruction Cycle – Execute Cycle • Data Processing: The CPU may perform some arithmetic or logic operation on data via the arithmetic-logic unit (ALU). • Control: An instruction may specify that the sequence of operation may be altered. For example, the program counter (PC) may be updated with a new memory address to reflect that the next instruction fetched, should be read from this new location. (eg. branch to new address based on a condition)

  15. Instruction Cycle – Execute Cycle • Remaining steps : to complete a LOAD instruction • Interpret the instruction and perform the action • Address portion of the instruction is loaded in MAR STEP 3: IR[address]  MAR • Actual data is copied into the accumulator STEP 4: MDR  A • Program Counter incremented STEP 5: PC + 1  PC

  16. LMC vs. CPU: Fetch and Execute Cycle

  17. Fetch-Execute Cycle: LOAD

  18. Fetch-Execute Cycle: ADD

  19. Fetch-Execute Cycle: STORE

  20. LMC Fetch-Execute SUBTRACT PC  MAR MDR  IR IR[addr]  MAR A – MDR  A PC + 1  PC IN PC  MAR MDR  IR IOR  A PC + 1  PC OUT PC  MAR MDR  IR A  IOR PC + 1  PC HALT PC  MAR MDR  IR BRANCH PC  MAR MDR  IR IR[addr]  PC BRANCH on Condition PC  MAR MDR  IR If condition false: PC + 1  PC If condition true: IR[addr]  PC

  21. Fetch-Execute Cycle Example Program Counter = 65 Value in Mem Location 65: 590 (LOAD 90) Value in Mem Location 66: 192 (ADD 92) Value in Mem Location 67: 390 (STORE 90) Value in Mem Location 90: 111 Value in Mem Location 92: 222

  22. Explanation – 1st Instruction LOAD 90 • PC -> MAR MAR now has 65 • MDR -> IR IR contains the instruction: 590 ------------------------ end of fetch • IR [address] -> MAR MAR now has 90, the location of the data • MDR -> A Move the value 111 from MDR to A • PC + 1 -> PC PC now points to 66

  23. Explanation – 2nd Instruction ADD 92 • PC -> MAR MAR now has 66 • MDR -> IR IR contains the instruction: 192 ------------------------ end of fetch • IR [address] -> MAR MAR now has 92, the location of the data • A + MDR -> A 111 in Accumulator + 222 in MDR = 333 into Accumulator • PC + 1 -> PC PC now points to 67

  24. Explanation – 3rd Instruction STORE 90 • PC -> MAR MAR now has 67 • MDR -> IR IR contains the instruction: 390 ------------------------ end of fetch • IR [address] -> MAR MAR now holds 90 • A -> MDR The value in A, 333 moves to memory location 90 • PC + 1 -> PC PC now points to 68 ------------------------ ready for next instruction

  25. Instruction Sets and Types

  26. Instruction Sets and Types • Instruction set is a complete collection of instructions that are understood by a CPU. • The instruction set is ultimately represented in binary machine code also referred to as object code. • The sets are represented by assembly codes to human programmer.

  27. Instruction Sets and Types

  28. Instruction Sets and Types • Elements of an instruction • Operation Code (opcode) • Usually 8 bits, used to indicate what to do. • Source Operand Reference(s) • Do the operation to the value at this address. • Result (Destination) Operand Reference(s) • Put the answer here • Next Instruction Reference (eg. JMP instruction)

  29. Instruction Sets and Types • Operands are used to specify which register, which memory location, or which I/O device. We’ll need some addressing scheme (immediate, register, memory addressing) for each. • In machine code, each instruction has a unique bit pattern. • For human consumption a symbolic representation is used called mnemonic. Examples of mnemonic are ADD, SUB etc.

  30. Instruction Sets and Types • The instruction set is grouped into a number of categories: • Data Movement (eg. load, store, Mov, XCHG) • Most common, greatest flexibility • Involve memory and registers • Arithmetic (eg. ADD, SUB, MUL,DIV) • Operators + - / * ^ • Integers and floating point

  31. Instruction Sets and Types • Boolean Logic • Often includes at least AND, XOR, and NOT • Single operand manipulation instructions (eg INC,DEC) • Negating, decrementing, incrementing, set to 0 • Bit manipulation instructions • Used for setting and resetting individual bits in a data word • Allows programmer to design their own Flags to test for conditions

  32. Instruction Sets and Types • Shift and rotate • Logical shift – zeros are shifted in to replace the bit spaces that have been vacated. • Arithmetic shift – multiply or divide by a power of 2. • Program control • Control the flow of a program • Jumps, branch, CALL, RETURN • Stack instructions • A stack is used to store data with the most recently used data will also be the first needed (LIFO structure) • Eg. Push, pop instructions

  33. Instruction Sets and Types • Multiple data instructions (eg. SIMD instruction) • Performs single operations on multiple pieces of data simultaneously. • Used for Multimedia apps (eg. Brightness of an image might be modified by multiplying the value of every pixel in the image by a common scale factor.) • I/O and machine control (eg. HALT) • Privileged instructions (Only available to the operating system only)

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