1 / 11

Latest Trends in FPGAs

Latest Trends in FPGAs. Sri Venkateswara College of Engineering and Technology Chittor, India, August 30 th 2013. Bharathwaj “Bart” Muthuswamy muthuswamy@msoe.edu Assistant Professor of Electrical Engineering Milwaukee School of Engineering (MSOE)

tirza
Download Presentation

Latest Trends in FPGAs

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Latest Trends in FPGAs Sri Venkateswara College of Engineering and Technology Chittor, India, August 30th 2013 Bharathwaj “Bart” Muthuswamy muthuswamy@msoe.edu Assistant Professor of Electrical Engineering Milwaukee School of Engineering (MSOE) BS (2002), MS (2005), PhD (2009) from Cal (University of California, Berkeley) Advisor: Dr. Leon O Chua, co-advisor: Dr. Pravin Varaiya http://www.harpgroup.org/muthuswamy

  2. Outline I. Trend 1: ASIC and FPGA on the same die II. Trend 2: High (Functional) Level Design Specification III. Trend 3: Space-Time IV. Conclusion V. References

  3. Trend 1: ASIC and FPGA on the same die Figure 1. Zynq-7000 [1]

  4. Trend 1: ASIC and FPGA on the same die (contd.) Figure 2. Cyclone V[2]

  5. Outline I. Trend 1: ASIC and FPGA on the same die II. Trend 2: High (Functional) Level Design Specification III. Trend 3: Space-Time IV. Conclusion V. References

  6. Trend 2: High (Functional) Level Design Specification Figure 3. DSP Builder Advanced BlocksetSimulink block diagram

  7. Trend 2: High (Functional) Level Design Specification (contd,) Figure 4. Simulation [3] vs. experimental results

  8. Outline I. Trend 1: ASIC and FPGA on the same die II. Trend 2: High (Functional) Level Design Specification III. Trend 3: Space-Time IV. Conclusion V. References

  9. Trend 3 : Space-Time Figure 5. Tabula ABAX architecture [4].

  10. Conclusion We have seen some of the latest trends in FPGA technology. In the next session, we will look at the FPGA architecture from one of the two major FPGA manufacturers: Altera.

  11. References • Xilinx Zynq homepage. http://www.xilinx.com/products/silicon-devices/soc/xa-zynq-7000.html Available, Online. Last accessed August 8th 2013. • Altera Cyclone V SOCs. http://www.altera.com/devices/processor/soc-fpga/cyclone-v-soc/cyclone-v-soc.html Available, Online. Last accessed August 8th 2013. • San-Um, W. and Srisuchinwong, B. “Highly Complex Chaotic System with Piecewise Linear Nonlinearity and Compound Structures”. Journal of Computers, Vol. 7, No. 4, pp. 1041-1047. April 2012. • Tabule Space-Time White Paper. http://www.tabula.com/products/pdf/WP003.pdf Available, Online. Last accessed August 8th 2013.

More Related