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Wireless Data and Power Transmission for In-Vivo Tissue Stimulation

Explore the functional design and specifications of a device capable of stimulating tissue in-vivo using wireless data and power transmission. Learn about the innovative techniques such as rectifier, regulator, and ramp generator employed in the system. Dive into the details of data path envelope detection, clock recovery, and timing control mechanisms for efficient operation.

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Wireless Data and Power Transmission for In-Vivo Tissue Stimulation

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Presentation Transcript

  1. Wireless data and power Brian McKinney Michael Vincent

  2. What we are doing • Ultimate goal is to create a device capable of precisely stimulating tissue in-vivo without connection to outside • Lack of external connection implies IC needs to derive both power and data from RF signal

  3. Transmitter • Not a mixed signal IC but needed for simulation and testing purposes • Generates random data • Frames random data (e.g. start/stop and parity bits) • Modulates carrier (ASK) with framed data

  4. Example

  5. Rectifier • Converts AC to DC • analog begin V(vout) <+ abs(vin); end

  6. Regulator • “Buck” type step down switching regulator

  7. Functional Design RampGenerator – Makes ramp signal with specified period and amplitude Regulator – Pulse Width Modulator, compares output voltage with ramp, adjusts duty cycle of square wave to produce desired output voltage

  8. Specs (theoretical) • Designed to source 25 mW at 3.3V • Switching frequency: 100 kHz • Inductor and capacitor values: • Make square wave coming from switch look DC • While supplying sufficient current to load during both phases (charge and discharge) • In our case, L = 1 uH and C = 10 uF (used switching frequency as a start and then a lot of trial and error) • Corner frequency ~ 50 kHz • Ripple current ~ 112.1 uA => 10.1% ripple

  9. So far…

  10. Data Path Envelope Detector Input: AM Signal (4MHz) Output: 100 Kbps “Dirty Data” Clock Recovery Input: 100 Kbps “Dirty Data” Output: 100 KHz Synchronous Clock Timing Control Inputs: 100 Kbps “Dirty Data” 100 KHz Clock Outputs: Clean Clock, Clean Data, Frame Strobe

  11. Envelope Detector

  12. Envelope Detector Simulation

  13. Clock Recovery

  14. Clock Recovery (Cont.)

  15. Timing Control • dirtyData shifted into register on rising edges of dirtyClk • Search for start frame • Two start bits • Eight zero data bits • Valid Parity and Stop bits • Enable Output and start sync counter

  16. Timing Control (Cont.) • Strobe signal indicates valid frame data is about to start • Valid clock and data (with frame info) shifted out • Invalid bytes will result in “dead time” on output clock, data and strobe lines

  17. Timing Results

  18. Conclusions and Q&A

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