DeFer : De ferred Decision Making Enabled Fixed-Outline F loorplann er

DeFer:Deferred Decision Making Enabled Fixed-Outline Floorplanner Jackey Z. YanChris Chu Dept. of Electrical & Computer Engineering Iowa State University Ames, IA 50010

Fixed-Outline Floorplanning Earliest Stage of VLSI Physical Design Enabling Hierarchical Design Important Part in Physical Synthesis

State-of-the-art Fixed-Outline Floorplanners

DeFer Overview Non-Stochastic Handling Hard and Soft Blocks Efficiently Promising Experimental Results BestHPWL All Academic Fixed-Outline Floorplanners Benchmarks: • GSRC • HB V.S. Best Runtime BestSuccess Rate • Main Principle: Deferred Decision Making (DDM) • Main Techniques: • Generalized Slicing Tree • Enumerative Packing (EP) • Block Swapping and Mirroring

Constraints of Ordinary Slicing Tree V B D E A H H C A B V C D E • Block orientation • Slice line direction (H/V) • Left-right or top-bottom relative order 5

Pick any point! Fixed-outline region B D E V A C H H H A A C V A B W D E DDM in Shape/Orientation • Defer the decision for subfloorplan (i.e., block) orientation until the end 6

DDM in Relative Order The relative order (left-right / top-down) between subfloorplans does not affect the shape curves V V A B B A V V V and A B B A A B H H BAV ABV B A A B W W Same shape curve • Decision on subfloorplan relative order will be made at the end to minimize HPWL 7

DDM in Slice Line Direction Two combine operators in ordinary slicing tree V V A A B B A A B B • Generalized combine operator H H and A A B B A B B B A A 8

Floorplans by Generalized Slicing Tree A B • Block orientation • Slice line direction • Left-right or top-bottom • relative order Deferred Decision Making (DDM) 9

C A B C A B H W=H C C h h C v W ( ii ) Flipping Shape Curve Operation for ? H H C W=H C h B A C v W W ( i ) Addition ( iii ) Merging

B D E A C DDM in Structure of Slicing Tree T1 T2 V H E E H C V D A B A B C D D C E A B Deferred the decision on the structureof generalized slicing tree!

H V V H H G H D B A F E C V H V G C H H V A F E D B E A C E F F C G A B D B G D Enumerative Packing (EP) HOW? K SK E A B F C G D Find shape curve capturing all slicing trees (i.e., all slicing floorplans) Given a set of blocks

T3 T4a T2 T4b Slicingtree structure 4 3 1 2 3 1 2 3 4 1 2 1 2 Block permutation A B A B C A B C D A B C D A B D D A C B A C B D A C B D A C D B B C A A D B C A D B C A D C B B C A D B C D A B D A C B D C A C D A B C D B A Simple Approach of Enumeration Too Expensive !!!

T4a T4b • Recursive relation: 4 K 3 P Q 1 2 3 4 1 2 Enumeration by Dynamic Programming • Example: To find shape curve for {A, B, C, D} • |K|=1: {A}, {B}, {C}, {D} • |K|=2: {A,B}, {A,C}, {A,D}, {B,C}, {B,D}, {C,D} • |K|=3: {A,B,C}, {A,B,D}, {A,C,D}, {B,C,D} • |K|=4: {A,B,C,D} redundant

Comparison on # of Operations Dynamic Programming (DP) based approach can significantly reduce runtime and memory.

Impact of EP on Packing Concerns of EP Memory and runtime when |K| is large EP considers packing only and ignores wirelength A practical approach: Recursive partitioning until each sub-circuit has only a few blocks Apply EP to the small sub-circuits K H SK W

Flow of DeFer 1. Partitioning 2. Combining Making Decisions on: • Subfloorplan Orientation 3. Back-Tracing • Slice Line Direction • Slicing Tree Structure 4. Swapping • Subfloorplan Relative Order 5. Compacting Not restricted to slicing floorplan

1. Partitioning Step 100 45 55 35 20 22 23 7 9 10 9 5 8 Recursively bi-partitioning • Generate smaller subcircuits • Minimize interconnections among subcircuits • Generate high-level slicing tree structure • Until # of blocks in each subcircuits ≤ maxN (maxN = 10 by default)‏

2. Combining Step Apply EP Combine ( ) shape curves recursively 100 45 55 20 35 22 23 Bottom-up 5 8 7 9 10 9 19

3. Back-Tracing Step Pick one candidate H Fixed- outline region Top-down W 20

4. Swapping Step • Try to switch two subfloorplans (blocks) to improve WL • Flow: • Rough Swapping • Detailed Swapping • Mirroring

E F Swapping and Mirroring Swapping Mirroring E F F E axis

5. Compacting Step • Compact towards the center • Improve WL • Not restricted to slicing floorplan Before After

Experiments Setup • All experiments run on a Linux machine withIntel Core Duo 1.86 GHz CPU and 2 GB memory • GSRC Benchmarks • Version with hard blocks only • # blocks: 100 ~ 300 • HB Benchmarks (derived from ISPD 98 benchmarks) • Mixture of hard and soft blocks (most hard blocks are square) • # blocks: 500 ~ 2000 • 3 different aspect ratios for fixed-outline region: 1, 2, 3 • Maximum white space: 10% • For each test case, average over 100 runs is reported

Result Summary (Normalized) • GSRC Benchmarks • HB Benchmarks [1] Saurabh N. Adya and Igor L. Markov. ICCD 2001 [2] Tung-Chieh Chen, Yao-Wen Chang and Shyh-Chang Lin. ICCAD 2005 [3] Song Chen and Takeshi Yosihmura. ISPD 2007 [4] Jason Cong, Michail Romesis and Joseph R. Shinnerl. ASP-DAC 2005

Conclusions • DeFer – high-quality, fast, robust and non-stochastic fixed-outline floorplanner • Principle of Deferred Decision Making (DDM) • Generalized Slicing Tree • Enumerative Packing (EP) • Block Swapping and Mirroring • Promising Experimental Results BestHPWL All Academic Fixed-outline Floorplanners Benchmarks: • GSRC • HB V.S. Best Runtime BestSuccess Rate

Future Work • Several techniques can be used to further improve the quality: • Terminal Propagation • Greedy Shifting • DeFer can be applied in other research: • Mixed-size Placement • Analog Placement with Various Geometry Constraints • Area Minimized Floorplanning • Floorplanner Integrated SoC Synthesis • Binary and source code of DeFer will be posted online soon: http://www.public.iastate.edu/~zijunyan/

Thank you!

DeFer : De ferred Decision Making Enabled Fixed-Outline F loorplann er