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Remote Firmware Down Load

Remote Firmware Down Load. Altera. Xilinx Virtex 5. Xilinx Virtex 5. Xilinx Virtex 5. EPROM. EPROM. EPROM. EPROM. Firmware Download Diagram for Front-End Readout Modules. VME. VME. Altera Stratix Control. Xilinx V4LX25. Altera. EPROM EPC16. EPROM XCF08. SRAM. EPROM EPC16.

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Remote Firmware Down Load

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  1. Remote Firmware Down Load

  2. Altera Xilinx Virtex 5 Xilinx Virtex 5 Xilinx Virtex 5 EPROM EPROM EPROM EPROM Firmware Download Diagram for Front-End Readout Modules VME VME Altera Stratix Control Xilinx V4LX25 Altera EPROM EPC16 EPROM XCF08 SRAM EPROM EPC16 VXS IsquareC Atmel uController Xilinx V4FX20 Xilinx V4LX25 VXS IsquareC EPROM XCF08 EPROM XCF08 ROC FADC250 TI Ethernet Firmware Files CTP SD

  3. FPGA Boot JTAG Links Remote Config FADC-250 Configuration Scheme VME Altera Stratix (control) SRAM Xilinx LX25 Xilinx XCF08 EPROM Altera CPLD JTAG Xilinx FX20 Xilinx XCF08 EPROM Altera EPC16 EPROM USB Xilinx LX25 Xilinx XCF08 EPROM PC FPGA Boot • Loading Configurarion After Installation • Control FPGA receives config. data via VME-64 bus and temporary stores to SRAM. Config. data for one or more FPGA can be received at once. • Control FPGA programs config. data into EPROM. • Control FPGA read back config data from EPROM to SRAM. • VME host (ROC) read and compare data. If OK, issue config command. • Control FPGA issues config command to EPROM to load new config. data to FPGA.. • Loading Configurarion During Code Development • Connect (Altera or Xilinx) JTAG cable • Set Dip Switch to select JTAG Chain • Run Altera Quartus or Xilinx Impact program to config Devices.

  4. FADC-250 Configuration Time FADC : Config data size: LX25 = .97744 Mbytes FX20 = .90528 Mbytes Stratix = 1.205 Mbyte VME transfer time (VME 30MByte/Sec): LX25 = .032 sec FX20 = .032 sec Stratix = .042 sec VME transfer for 1 FADC (all FPGA) to Control: .14 sec JTAG transfer time (JTAG clock of 3MHz) LX25 = 3 sec FX20 = 3 sec Stratix = 4 sec Time to erase FLASH: LX25, FX20 = 9 sec Stratix = 20.5 sec Time to program FLASH LX25 = 31.3 sec FX20 = 25.0 sec Straitx = 76.5 sec Total ~= 238 sec. ~= 4 minutes.

  5. Xilinx XCF16 EPROM Xilinx LX50 Xilinx XCF16 EPROM Xilinx LX50 Xilinx XCF32 EPROM Xilinx LX110 FPGA Boot JTAG Links CTP Configuration Scheme VXS IsquareC Remote Config • Loading Configurarion After Installation • LX110 config. data via VXS IsquareC and temporary stores to RAM inside FPGA. Config. Data has to be segmented due to limited RAM. • LX110 programs config. data into EPROM. • LX110 read back config data from EPROM to SRAM. • VME host (ROC) read and compare data. If OK, send next segment. • VME host (ROC) issues config command when all segments are stored in ROM. • LX110 issues config command to EPROM to load new config data to FPGA.. • Loading Configurarion During Code Development • Connect Xilinx JTAG cable • Run Xilinx Impact program to config Devices.

  6. CTP Configuration Time CTP : Config data size: LX50 = 1.57 Mbytes LX110 = 3.64 Mbytes VME transfers to TI (VME 30MByte/Sec): LX50 = .053 sec LX110 = .122 sec TI transfers to CTP (IsquareC 34.43Kbytes/Sec write; 40.08 Kbytes/Sec read (1) ): LX50 = 56 sec (wr); 40 sec (rd) LX110 = 106 sec (wr); 91 sec (rd) JTAG transfer time (JTAG clock of 3MHz) LX50 = 5.2 sec LX110 = 12 sec Time to erase FLASH: LX50 = 16 sec LX110 = 36 sec Time to program FLASH LX50 = 50 sec LX110 = 117 sec Total ~= 720 sec. ~= 12 minutes. (1) Documentation of I2C Protocol Project, Sebouh Paul

  7. Altera Control FPGA AHDL Operating Code VME IFACE SRAM Select CMD REGS EPROM OP_CODE SEQUENCER Select EPROM OP-CODE TABLE Altera CPLD JTAG IFACE JTAG VHDL Code to Remotely Configure FPGA VHDL Block Diagram to Remotely Configure FADC-250 VME BUS • Remote Configurarion Sequence • VME host (ROC) write configuration data for one or more FPGA to SRAM (memory map TBD). • VME host write CMD Registers to initiate EPROM stored. • VHDL Code takes over control of SRAM. Read config. data from SRAM, send OP-Code to EPROM, and stores config data to EPROM. After store, read back EPROM data to SRAM. • VHDL code relinquishes control of SRAM and signals VME host. • VME host verifies EPROM stored data. If OK, write CMD Register to initiate FPGA config. • VHDL Code issues config command to EPROM to load new config data to FPGA.

  8. VHDL Block Diagram to Remotely Configure CTP LX110 FPGA VHDL Operating Code IsquareC Bus IsquareC IFACE RAM Select CMD REGS EPROM OP_CODE SEQUENCER EPROM OP-CODE TABLE Xilinx XCF16 EPROM Xilinx XCF16 EPROM Xilinx XCF32 EPROM JTAG IFACE JTAG VHDL Code to Remotely Configure FPGA • Remote Configurarion Sequence • VME host (ROC) write configuration data in segments (Host to TI and then TI to LX110). • VME host write CMD Registers to initiate EPROM stored. • VHDL Code takes over control of SRAM. Read config. data from SRAM, send OP-Code to EPROM, and stores config data to EPROM. After store, read back EPROM data to SRAM • VHDL code relinquishes control of SRAM and signals VME host. • VME host verifies EPROM stored data. If OK, repeat for all segmens. • When all segments are done, twrite CMD Register to initiate FPGA config. • VHDL Code issues config command to EPROM to load new config data to FPGA.

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