Learning-by-gaming in HW/SW codesign

1. EWME 2010-05-11 Learning-by-gaming in HW/SW codesign Vadim Pesonen, Maksim Gorev, Kalle Tammemäe

2. Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements EWME 2010-05-11 Learning-by-gaming in HW/SW codesign

3. Modelling languages and tools Design space Estimate and analyze to partition Predefined IP cores Accomplish team tasks EWME 2010-05-11 Introduction and course objectives • Laboratory works for HW/SW codesign course • Overcome complexity with entertaining practical works • Learn by designing games Students must be aware of/be able to:

4. Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements EWME 2010-05-11 Agenda

5. English as the primary language Materials available online Affordable development boards Consider students’ background knowledge Introduction to HDLs VLSI synthesis Digital system design System-on-a-chip design Numerous projects EWME 2010-05-11 Planning the course and practical works

6. Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements EWME 2010-05-11 Agenda

7. 4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design Various HW/SW ratios EWME 2010-05-11 Laboratory work assignments

8. 4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design Several HW/SW partitions EWME 2010-05-11 Laboratory work assignments

9. 4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design Various HW/SW ratios EWME 2010-05-11 Laboratory work assignments

10. 4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Xilinx PicoBlaze soft-core processor Advanced – complex design Various HW/SW ratios EWME 2010-05-11 Laboratory work assignments

11. 4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design Various HW/SW ratios EWME 2010-05-11 Laboratory work assignments

12. Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements EWME 2010-05-11 Agenda

13. + Good course objective coverage + Generally positive students’ reaction + Strong team spirit during practical works – Insufficient practical work guides – Complexity gap between assignments - 1/3 failed the laboratory tasks – Used soft-core processor insufficient EWME 2010-05-11 Obtained results

14. Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements EWME 2010-05-11 Agenda

15. Address negative feedback Employ more powerful soft-core processors Xilinx MicroBlaze OpenRISC Coffee RISC core Extend board usage Different FPGA platforms EWME 2010-05-11 Future enhancements