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Ontwerp van een 4-bit modulaire opteller in VHDL

HOJ95: Exercise 1 - structural VHDL (gate level) February 28, 2005. Ontwerp van een 4-bit modulaire opteller in VHDL. Optelling INPUT: 0 ≤ x, y < p OUTPUT: t = x + y mod p t1 = x + y t2 = t1 – p if t2 > 0 t = t2 else t = t1. Algoritme. t = x + y mod p. Aanpak.

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Ontwerp van een 4-bit modulaire opteller in VHDL

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  1. HOJ95: Exercise 1 - structural VHDL (gate level) February 28, 2005 Ontwerp van een 4-bit modulaire opteller in VHDL

  2. Optelling INPUT: 0 ≤ x, y < p OUTPUT: t = x + y mod p t1 = x + y t2 = t1 – p if t2 > 0 t = t2 else t = t1 Algoritme t = x + y mod p

  3. Aanpak • 6-bit opteller/aftrekker • 4-bit modulaire opteller Data input Data output Opteller/ aftrekker Datapad Controle signalen Status signalen Controle output Controle input FSM Controle blok

  4. 1. 4-bit opteller architecture b a a(3) b(3) a(1) b(1) a(0) b(0) a(2) b(2) ha ha = half adder fa fa fa ha carry sum b c a sum(4) sum(2) sum(1) sum(3) sum(0) fa = full adder fa carry_i(2 downto 0) carry sum

  5. a en b kunnen zowel positief als negatief zijn 2’s complement notatie 6-bit ingangen, 6-bit uitgang (1ste bit is tekenbit) extra ingang die aangeeft of we optellen of aftrekken: o_a 2. 6-bit opteller/aftrekker entity 6 a 6 6 b sum o_a entity opaf_6bit is port( a, b: in std_logic_vector(5 downto 0); o_a: in std_logic; sum: out std_logic_vector(5 downto 0)); end opaf_6bit;

  6. 1. 6-bit opteller/aftrekker architecture entity fa is port( a, b, c: in std_logic; sum, carry: out std_logic); end fa; architecture arch_fa of fa is begin sum <= a xor b xor c; carry <= (a and b) or (a and c) or (b and c); end arch_fa;

  7. 2. 6-bit opteller/aftrekker architecture b_i(5 downto 0) b(5) b(4) b(3) b(2) b(1) b(0) a(5) a(4) a(3) a(1) a(0) a(2) o_a fa fa fa fa fa sum(5) sum(2) sum(1) sum(4) sum(3) sum(0) carry_i(4 downto 0)

  8. 2. 6-bit opteller/aftrekker architecture architecture arch_opaf_6bit of opaf_6bit is component fa port( a, b, c: in std_logic; sum, carry: out std_logic); end component; signal carry_i: std_logic_vector(4 downto 0); signal b_i: std_logic_vector(5 downto 0); begin b_i(0) <= b(0) xor o_a; b_i(1) <= b(1) xor o_a; b_i(2) <= b(2) xor o_a; b_i(3) <= b(3) xor o_a; b_i(4) <= b(4) xor o_a; b_i(5) <= b(5) xor o_a; inst_fa0: fa port map(a(0), b_i(0), o_a, sum(0), carry_i(0)); inst_fa1: fa port map(a(1), b_i(1), carry_i(0), sum(1), carry_i(1)); inst_fa2: fa port map(a(2), b_i(2), carry_i(1), sum(2), carry_i(2)); inst_fa3: fa port map(a(3), b_i(3), carry_i(2), sum(3), carry_i(3)); inst_fa4: fa port map(a(4), b_i(4), carry_i(3), sum(4), carry_i(4)); sum(5) <= a(5) xor b_i(5) xor carry_i(4); end arch_opaf_6bit;

  9. 3. 4-bit modulaire opteller rst idle 0 start 1 tel_op reductie 1 0 t2_uit t2 > 0 t1_uit

  10. 3. 4-bit modulaire opteller next-state process comb: process(huidige_toestand, start, t2) begin case huidige_toestand is when idle => if start = '0' then volgende_toestand <= idle; else volgende_toestand <= optelling; end if; when optelling => volgende_toestand <= reductie; when reductie => if t2(5) = '0' then volgende_toestand <= t2_uit; else volgende_toestand <= t1_uit; end if; when t1_uit => volgende_toestand <= idle; when t2_uit => volgende_toestand <= idle; when others => volgende_toestand <= idle; end case; end process;

  11. 3. 4-bit modulaire opteller clock process seq: process(rst, clk) begin if rst = '1' then huidige_toestand <= idle; elsif clk'event and clk = '1' then huidige_toestand <= volgende_toestand; end if; end process;

  12. 3. 4-bit modulaire opteller output process outp: process(huidige_toestand, x, y, p, sum, t1, t2) begin case huidige_toestand is when idle => t <= (others => '0'); done <= '0'; when optelling => a <= "00" & x; b <= "00" & y; o_a <= '0'; t1 <= sum; done <= '0'; when reductie => a <= t1; b <= "00" & p; o_a <= '1'; t2 <= sum; done <= '0'; when t1_uit => t <= t1(3 downto 0); done <= '1'; when t2_uit => t <= t2(3 downto 0); done <= '1'; when others => null; end case; end process;

  13. Optelling INPUT: 0 ≤ x, y < p OUTPUT: t = x + y mod p t1 = x + y t2 = t1 – p if t2 > 0 t = t2 else t = t1 Algoritme – Opteller en Aftrekker t = x ± y mod p Aftrekking INPUT: 0 ≤ x, y < p OUTPUT: t = x – y mod p • t1 = x – y • t2 = t1 + p • if t1 > 0 t = t1 else t = t2

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