1 / 12

SDHCAL Power pulsing tests status in lyon C. Combaret, for the IPNL team

SDHCAL Power pulsing tests status in lyon C. Combaret, for the IPNL team. As discussed with HR2 designers : Record (reference) Scurves and Bias levels with no capacitor removed Enable PP hardware on DIF (use of Mezzanine pin 1) Enable PP in DIF firmware : PowerOn_x = register OR Mezzanine_1

tanya-finley
Download Presentation

SDHCAL Power pulsing tests status in lyon C. Combaret, for the IPNL team

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. SDHCAL Power pulsing tests status in lyon C. Combaret, for the IPNL team

  2. As discussed with HR2 designers : Record (reference) Scurves and Bias levels with no capacitor removed Enable PP hardware on DIF (use of Mezzanine pin 1) Enable PP in DIF firmware : PowerOn_x = register OR Mezzanine_1 Try PP with no capacitor removed Record analog bias signal Remove Capacitors on biases of 1 HR2 step by step and check Record analog bias signal Record Scurves Remove Capacitors on biases of all asics and check again Record analog bias signal Record Scurves Power pulsing on Hardroc 2 ASU : method

  3. Hardware setup Trg ext (Lemo2) HP33220A Enable PP (Mezzanine) Sync Trg ext Enable Acq (Mezzanine) HP33250A DIF Sync Trg ext Ctest HP81104 Lemo1 Lemo2 Enable PP Enable Acq Lemo1 cTest

  4. Power pulsing on Hardroc 2 ASU : method

  5. Power pulsing on Hardroc 2 ASU : preliminary results PowerOn Command Vbg (BandGap) 10us Capacitors removed on one asic (first of the ASU)

  6. Power pulsing on Hardroc 2 ASU : preliminary results PowerOn Command Vth 0 <20us Capacitors removed on one asic (first of the ASU)

  7. Power pulsing on Hardroc 2 ASU : preliminary results Trig_ext (Lemo1) 50 µs Enable Acq Enable PP Vth2 Power Off Power On Capacitors removed on all asics

  8. Power pulsing on Hardroc 2 ASU : preliminary results DAC1Min = 80 DAC1Max =400 DAC1Step=1 GainMin = 128 GainMax = 128 GainStep=1 Injection=0.5V Pedestal looks roughly OK Injected channel seems rougly OK BUT strange behaviour for injected pads.  Because of slow control bug in HR2, some (many) SLC configurations can not be used

  9. Power pulsing on Hardroc 2 ASU : preliminary results Asic 1 DAC1Min = 80 DAC1Max =400 DAC1Step=1 GainMin = 128 GainMax = 128 GainStep=1 Injection=0.5V After correction, data seem more correct… But this Scurve is very preliminary, comparisons must be made with results obtained before power pulsing.

  10. DIF (For J. Prast, LAPP) VHDL firmware1 for Hardroc1 Micromegas VHDL firmware2 for Hardroc1 RPC VHDL firmware3 for Dirac2 Micromegas VHDL firmware4 for Hardroc2 Micromegas VHDL firmware5 for Calice DAQ Test

  11. DHCAL DIF Production (For J. Prast, LAPP) 120 DIF have to be produced for the m3 (+ spares ie 140 ?). The DIF will be produced as they are currently. The board works quite well. We do not have time to make a new prototype (schedule + manpower). Boards will be produced and tested for beginning of fall 2010. Some boards can be available before if required (> end of spring)

  12. Thank you for your attention

More Related