EDMA3 Keystone SoC Devices

EDMA3 Keystone SoC Devices

Agenda • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

What is DMA? • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

Why Use DMA? D0 buf_0 buf_1 D1 D2 D3 • The primary function of DMA is to move data without direct CPU involvement. • What information does a DMA controller need to perform a transfer? • Source address • Destination address • Length (or size) • What options might be useful to perform the transfer? • Do you want to interrupt the CPU when the transfer is complete? • Is this transfer synchronized to an event (like the McBSP RCV buffer is full)? • How do the source and destination addresses update? (same, +1, -1, +4 ?)

EDMA3 EVTx TC0 Chain DMA TC1 Manual Q1 Qn Q0 Q2 TC2 TeraNet TCn QDMA Trigger Word DMA in KeyStone Devices There are MANY forms of DMA (Direct Memory Access) in the KeyStone Architecture. • EDMA3 – Enhanced DMA handles M DMA CHs and XQDMA CHs • DMA – M Channels that can be triggered manually or by events/chaining • QDMA – Xchannels of Quick DMA triggered by writing to a trigger word Resources connected to TeraNet • IDMA – 2 CHs of Internal DMA (PeriphCfg, Xfr L1 ↔ L2) IDMA L1D L2 Ch0 Ch1 L1 L2 PERIPH • Peripheral DMAs– Each master device hooked to the TeraNet • has its own DMA (PktDMA) (e.g. SRIO, EMAC, etc.)

EDMA Architecture • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

Queue PSET 0 PSET 1 Q0 Q1 Q2 PSET X Qm EDMA3 Architecture En E1 E0 CC TC EvtReg (ER) Evt Enable Reg(EER) TC0 .. . TC1 TRSubmit Evt Set Reg(ESR) Data TeraNet TC2 TCm Chain EvtReg(CER) EarlyTCC Int Pending Reg – IPR CompletionDetection NormalTCC Int Enable Reg – IER Memory Protection Global Interrupt & Region Interrupt (0-n)

Shadow Regions and Memory Protection • Multi-level protection: • Regions restrict access to the channels from the peripheral masters. • Memory Protection provides restricted access to different memory spaces within the device. • Each region has a copy of the channel configuration registers to configure the channels allocated to the specific region (DRAEn and DRAEHn, QRAEn). • In addition to the shadow regions, there is a global region access to the Channel Controller. • Memory protection is provided by setting the privilege level, requestor, and types of access allowed for each region (MPPAn and MPPAG). • Each shadow region is also associated with a completion interrupt that can be tied to different interrupt events.

Shadow Region

Definition of EDMA3 Terminology • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

Original Data Block Copied Data Block DMA Direct Memory Access (DMA) Goal : Examples : • Controlled by : • Copy from memory to memory – HARDWARE memcpy(dst, src, len); • Faster than CPU LD/ST. One INT per block vs. one INT per sample • Import raw data from off-chip to on-chip before processing. • Export results from on-chip to off-chip afterward. • Transfer Configuration (i.e., Parameter Set - aka PaRAM or PSET) • Transfer configuration primarily includes 8 control registers. Source BCNT Length ACNT Transfer Configuration Destination

Block Frame Frame 1 Elem 1 Frame 2 Elem 2 .. .. Elem N Frame M B Count C Count B Count (# Elements) C Count (# Frames) A Count (Element Size) 31 31 16 16 15 15 0 0 How Much to Move? Element A Count (# of contiguous bytes) Transfer Configuration Options Source B A Transfer Count Destination Index Cnt Reload Link Addr Index Index Rsvd C 9

Example: How to VIEW the Transfer • Let’s start with a simple example. • We need to transfer 12 bytes from “here” to “there.” NOTE: These are contiguous memory locations 8-bit • What is ACNT, BCNT, and CCNT? Hmmm…. • You can view the transfer several ways: ACNT = 1 BCNT = 4 CCNT = 3 ACNT = 2 BCNT = 2 CCNT = 3 ACNT = 12 BCNT = 1 CCNT = 1 = 12 • Which “view” is the best? Well, that depends on what your system needs and the type of sync and indexing (covered later…)

Synchronization • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

A – Synchronization • An event (i.e.,McBSP receive register full) triggersthe transfer of exactly 1 array of ACNT bytes (2 bytes) • Example: McBSP tied to a codec. You want to sync each transfer of a 16-bit word to the receive buffer being full or the transmit buffer being empty. EVTx EVTx EVTx Frame 1 Array1 Array2 Array BCNT Frame 2 Array1 Array2 Array BCNT Frame CCNT Array1 Array2 Array BCNT

AB – Synchronization • An event triggers a two-dimensional transfer of BCNT arraysof ACNT bytes (A*B). • Example: Line of video pixels; Each line has BCNT pixels consisting of 3 bytes each – Y, Cb, Cr EVTx Frame 1 Array1 Array2 Array BCNT Frame 2 Array1 Array2 Array BCNT Frame CCNT Array1 Array2 Array BCNT

Indexing • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

A-Sync EVTx EVTx EVTx . . ‘BIDX ‘CIDXA . . Indexing: ‘BIDX, ‘CIDX • EDMA3 has two types of indexing: ‘BIDX and ‘CIDX • Each index can be set separately for SRC and DST (next slide…) • ‘BIDX= index in bytes between ACNT arrays (same for A-sync and AB-sync) • ‘CIDX= index in bytes between BCNT frames (different for A-sync vs. AB-sync) • ‘BIDX/’CIDX: signed 16-bit, -32768 to +32767 AB-Sync EVTx . . ‘BIDX CIDXAB . . • CIDX distance is calculated from the starting address of the previouslytransferred block (array for A-sync, frame for AB-sync) to the next frame tobe transferred.

1 3 5 7 9 11 13 15 Indexed Transfers • EDMA3 has 4 indexes allowing higher flexibility forcomplex transfers: • SRCBIDX = # bytes between arrays (Ex: SRCBIDX = 2) • SRCCIDX = # bytes between frames (Ex: SRCCIDXA = 2, SRCCIDXAB = 4) • Note: ‘CIDX depends on the synchronization used – “A” or “AB” • DSTBIDX = # bytes between arrays (Ex: DSTBIDX = 3) • DSTCIDX = # bytes between frames (Ex: DSTCIDXA = 5, DSTCIDXAB = 8) SRCBIDX DSTBIDX 1 3 DSTCIDXA SRCCIDXA 5 7 SRC (8-bit) 9 11 (contiguous) DST (8-bit) (contiguous)

Example: Using Indexing • Remember this example? For each “view”, fillin the proper SOURCE index values: NOTE: These are contiguous memory locations 8-bit ACNT = 1 BCNT = 4 CCNT = 3 ACNT = 2 BCNT = 2 CCNT = 3 ACNT = 12 BCNT = 1 CCNT = 1 ‘BIDX = 1 ‘CIDXA = 1 ‘CIDXAB = 4 ‘BIDX = 2 ‘CIDXA = 2 ‘CIDXAB = 4 ‘BIDX = N/A ‘CIDXA = N/A ‘CIDXAB = N/A • Which “view” is the best? Well, that depends on what you are transferring from/to and which sync mode is used.

Example to Summarize • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

Options Solution Source Options BCNT ACNT &pixel_7 Destination 3 4 DSTBIDX SRCBIDX &myDest BCNTRLD LINK 8 bits 4 6 DSTCIDX SRCCIDX = BCNT 0xFFFF (later) RSVD CCNT 0 0 31 0 RSVD 1 31 0 Parameters for a Single Block Transfer 8-bit Pixels 8 7 &myDest: Goals: 0 1 2 3 4 5 9 8 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 10 9 12 13 14 15 16 17 10 11 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) 20 21 22 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer?

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 7 8 &myDest: Goals: 0 1 2 3 4 5 8 9 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible(single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 9 10 12 13 14 15 16 17 11 10 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 21 22 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 7 8 &myDest: Goals: 0 1 2 3 4 5 8 9 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data,AB-sync) 6 7 8 9 10 11 9 10 12 13 14 15 16 17 11 10 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 21 22 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 8 7 &myDest: Goals: 0 1 2 3 4 5 8 9 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data,AB-sync) 6 7 8 9 10 11 10 9 12 13 14 15 16 17 10 11 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 AB-sync 21 22 3 4 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 1 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 8 7 &myDest: Goals: 0 1 2 3 4 5 8 9 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 10 9 12 13 14 15 16 17 10 11 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 A-sync? 21 22 4 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 8 7 &myDest: Goals: 0 1 2 3 4 5 8 9 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 10 9 12 13 14 15 16 17 10 11 18 19 20 21 22 23 13 - 11 24 25 26 27 28 29 14 - 12 (Src: &pixel_7) 15 - 13 Note: data values arein contiguous memory 16 - 14 19 - 15 Param Set (active) Solution 20 - 16 A-sync? 21 - 17 22 - 18 12 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 8 7 &myDest: Goals: 0 1 2 3 4 5 8 9 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 9 10 12 13 14 15 16 17 10 11 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 AB-sync 21 &pixel_7 22 3 4 &myDest • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 1 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 7 8 &myDest: Goals: 0 1 2 3 4 5 9 8 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 10 9 12 13 14 15 16 17 11 10 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 AB-sync 21 &pixel_7 22 3 4 &myDest 6 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 1 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 7 8 &myDest: Goals: 0 1 2 3 4 5 9 8 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 9 10 12 13 14 15 16 17 11 10 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 AB-sync 21 &pixel_7 22 3 4 &myDest 4 6 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 1 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 7 8 &myDest: Goals: 0 1 2 3 4 5 8 9 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 10 9 12 13 14 15 16 17 10 11 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 AB-sync 21 &pixel_7 22 3 4 &myDest 4 6 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 0 0 1 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 7 8 &myDest: Goals: 0 1 2 3 4 5 8 9 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 10 9 12 13 14 15 16 17 11 10 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 AB-sync 21 &pixel_7 22 3 4 &myDest 4 6 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? BCNT or any 0 0 1 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 7 8 &myDest: Goals: 0 1 2 3 4 5 8 9 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible(single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 10 9 12 13 14 15 16 17 11 10 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 AB-sync 21 &pixel_7 22 3 4 &myDest 4 6 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 3 0xffff 0 0 1 31 0

Options Source BCNT ACNT Destination DSTBIDX SRCBIDX BCNTRLD LINK 8 bits DSTCIDX SRCCIDX RSVD CCNT 31 0 Parameters for a Single Block Transfer 8-bit Pixels 7 8 &myDest: Goals: 0 1 2 3 4 5 8 9 • Transfer a block of 8-bit pixels from &pixel_7 to &myDest • Transfer all pixels as quickly as possible (single EVTx – xfr all data, AB-sync) 6 7 8 9 10 11 10 9 12 13 14 15 16 17 11 10 18 19 20 21 22 23 13 24 25 26 27 28 29 14 (Src: &pixel_7) 15 Note: data values arein contiguous memory 16 19 Param Set (active) Solution 20 AB-sync 21 &pixel_7 22 3 4 &myDest 4 6 • Why can’t we use ACNT=1? • How does this transfer work inside the EDMA? • What happens when the transfer completes? • How do you program this transfer? 3 0xffff 0 0 1 31 0

Channel OPTions Register • The Options register contains bit fields that configure how the channel operates. • Each field has a corresponding description in the Param Setup code comments. • TCC = Transfer Complete Code to signal completion • SYNCDIM = A-sync or AB-sync • PRIV = Privilege level of the host that can program the PSET • PRIVID = Privilege ID of the host that program the PSET • ITCCHEN = Intermediate Transfer Completion Chaining Enable • TCCHEN = Transfer Completion Chaining Enable • ITCINTEN = Intermediate Transfer Completion Interrupt Enable • TCINTEN = Transfer Completion Interrupt Enable • TCC = Transfer Completion Code • TCCMODE = Point at which the transfer is considered to be complete. • SAM = Source Address Mode • DAM = Desitination Address Mode • FWID = FIFO Width • STATIC = Option to enable changing PSET

Trigger Mechanisms • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

Done 1 2 3 4 5 6 T (xfer config) 7 8 8 9 9 10 10 11 11 12 13 14 15 16 17 18 E (event) A (action) 19 20 21 22 23 24 25 26 27 28 29 30 Options Source B A Transfer Count Destination Index Cnt Reload Link Addr Index Index Rsvd C EDMA3 Basics Revisited • Count:How many items to move • A, B, and C counts • Addresses: The source & destination addresses • Index:How far to increment the src/dst after each transfer T (xferconfig) • Event:Triggersthe transfer to begin • Transfer:The transfer config describes the transfers to be executed when triggered. • Resulting Action: What do you want to happen after the transfer is complete?

Event Sync from peripheral 1 2 3 SPI EDMA3 SPIREVT SPIXEVT Start Ch Xfr ER EER How to TRIGGER a Transfer • There are 3 ways to trigger an EDMA transfer: ER = Event Register (flag) EER = Event Enable Register (user) Manually trigger the channel to run Application Channel y ESR = Event Set Register (user) Set Ch #y; Start Ch Xfr ESR Chain event from another channel (more details later…) Channel x Channel y TCCHEN = TC Chain Enable (OPT) TCCHEN_EN TCC = Chy Start Ch Xfr CER 28

Action Mechanisms • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

Generate EDMA Interrupt (Setting IERbit) EDMA Channels EDMA Interrupt Generation Channel # Options TCC IPR IER 0 0 TCINTEN=0 TCC=0 IER0 = 0 1 0 TCC=1 TCINTEN=0 IER1 = 0 EDMA3CC_INT . . . 1 TCINTEN=1 TCC=14 IER14 = 1 N 0 TCINTEN=0 TCC=N IERN= 0 Options TCINTEN TCC IER – EDMA Interrupt Enable Register (NOT the CPU IER)IPR – EDMA Interrupt Pending Register (set by TCC) 20 17 12 • Use EDMA3 Low-Level Driver (LLD) to program the EDMA IER bits NChannels and ONE interrupt? How do you determine WHICH channel completed?

Read IPR bits Determine which one is set Call corresponding handler(ISR) in Fxn Table EDMA Interrupt Dispatcher Here’s the interrupt chain from beginning to end: 1. An interrupt occurs 2. Interrupt Selector 3. HWI_INT5 Properties HWI_INT5 EDMA3CC_GINT 4. EDMA Dispatcher Function 5. ISR (interrupt handler) void edma_rcv_isr (void) { SEM_post (&semaphore); } How does the ISR Fxn Table (in #4 above) get loaded with the proper handler Fxn names? Use EDMA3 LLD to program the proper callback fxn for this HWI.

Linking • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

Done T (xfer config) E (event) A (action) Options Source T (xferconfig) B A Transfer Count Destination Index Cnt Reload Link Addr Index Index Rsvd C Linking – “Action” – Overview Alias: “Re-load” “Auto-init” • Need: auto-reload channel with new config • Ex1: do the same transfer again • Ex2: ping/pong system • Solution: use linking to reload Chconfig • Concept: • Linking two or more channels together allowsthe EDMA to auto-reload a new configurationwhen the current transfer is complete. • Linking still requires a “trigger” to start thetransfer (manual, chain, event). • You can link as many PSETs as you like – it is only limited by the #PSETs on a device. • How does linking work? • User must specify the LINK fieldin the config to link to another PSET. • When the current xfr (0) is complete,the EDMA auto reloads the newconfig (1) from the linked PSET. Config 0 Config 1 reload LINK LINK 1 NULL NOTE: Does NOT start transfer!!

Chaining • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

Event sync from peripheral 1 2 3 McASP0 EDMA3 RRDY XRDY Start Ch Xfr ER EER Triggering Transfers Revisited There are 3 ways to trigger an EDMA transfer: ER = Event Register (flag) EER = Event Enable Register (user) Manually trigger the channel to run Application Channel y ESR = Event Set Register (user) Set Ch #y; Start Ch Xfr ESR  Chain event from another channel Channel x Channel y TCCHEN = TC Chain Enable (OPT) TCCHEN_EN TCC = Chy Start Ch Xfr CER

Done T (xfer config) E (event) A (action) Options Source T (xfer config) B A Transfer Count Destination Index Cnt Reload Link Addr Index Index Rsvd C Chaining – “Action” & “Event” – Overview • Need: When one transfer completes, trigger another transfer to run • Ex: ChX completes, kicks off ChY • Solution: Use chaining to kick off next xfr • Concept: • Chaining actually refers to both both an action and an event – the completed ‘action’ from the 1st channel is the ‘event’ for the next channel • You can chain as many Chan’s as you like – it is only limited by the #Ch’s on a device • Chaining does NOT reload current Chan config – that can only be accomplished by linking. It simply triggers another channel to run. • How does chaining work? • Set the TCC field to match the next (i.e. chained) channel # • Turn ON chaining • When the current xfr (X) is complete,it triggers the next Ch (Y) to run Ch X Ch Y Y ? Done ? TCC TCC RUN Y EN DIS Chain EN Chain EN

QDMA • What is DMA? • EDMA Architecture • Definition of EDMA3 Terminology • Synchronization • Indexing • Example to Summarize • Trigger Mechanisms • Action Mechanisms • Linking • Chaining • QDMA • EDMA3 LLD Review

Quick DMA (QDMA) • QDMA is used for simple transfers where syncing to an eventis not required. Address/count updates and linking are notperformed. CCNT = 1 (single event transfer). • A transfer can be triggered by two methods:(1) writing to a trigger word (2) using the EDMA3 LLD. • It is “quick” because the CPU can initiate a transfer with asfew as ONE write to a channel register. • How does it work? • QDMA channel is “auto-triggered” when CPU writes to the “trigger” word • Eliminates the need to write to PSET and kick off transfer w/ separate write to ESR • Selection of the trigger word allows CPU to modify only words of interest in a PSET • Assumes OPT.STATIC = 1. Count and address updates and linking NOT performed. • Example: • If ACNT/BCNT/CCNT are typically static for a given algorithm, but SRC is differentfor each transfer, then SRC could be defined as the trigger word. CPU can initiate atransfer with a single write to the SRC address for the specified PSET.

EDMA3 Keystone SoC Devices