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ITRS Roadmap Design + System Drivers 2006-7 Worldwide Design TWG. What’s New in 2005 Design & System Drivers. First Design For Manufacturability roadmap DFM roadmap tool Interface with other groups. First worldwide quantitative design technology roadmap System-level Logic/circuit/layout

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Itrs roadmap design system drivers 2006 7 worldwide design twg
ITRS Roadmap Design + System Drivers2006-7 Worldwide Design TWG


What s new in 2005 design system drivers
What’s New in 2005 Design & System Drivers

  • First Design For Manufacturability roadmap

    DFM roadmap tool

    Interface with other groups

  • First worldwide quantitative design technology roadmap

    System-level

    Logic/circuit/layout

    Verification

    DFT

    DFM

  • New SoC model captures emerging market driver

    Consumer driver

    improves alignment

    with other roadmaps

  • Emerging SoC fabric drivers updated

    Analog & MIxed-signal

    Embedded memory

In next 10 years, new drivers and technology limitations will require design technology overhaul at all abstraction levels




Design content organization
Design: Content organization

  • Promotion of key design challenges

    • Small subset of them as top-level ORTC table

General

Selection

Productivity

Power

DFM

Interference

Reliability

Mapping

System

design

Logic/circuit

Physical D

Design

verification

Design

Test

DFM

(new)


New overall design technology challenges
New:Overall Design Technology Challenges


New overall design technology challenges1
New:Overall Design Technology Challenges



System level requirements
System-Level Requirements

Source: Wolfgang Rosenstiel’s Team




Dfm variability framework
DFM  Variability Framework

Actual (bottom-up) / required (top-down) variability

Performance (delay)

Power (energy)

“Gate” delay (power)

“Wire” delay (power)

Intermediate parameters

Intermediate parameters

(Vdd, T)

Rsheet

Vt

Leff

tOX

NA

Weff

L

t

W

tILD

Other TWGs (PIDS, Interconnect, etc.)


Roadmapping dfm issues inc variability
Roadmapping DFM Issues inc. Variability

  • Current recommendation

    • Not to extend 10% CD control beyond 15%

    • Below 15% still unclear  12% possibly acceptable



Itrs system drivers market and application alignment
ITRS System Drivers Market and Application Alignment

  • ITRS Design Group focuses on roadmapping

    • Design Technology challenges and solutions

    • Drivers for Silicon Systems design

  • ITRS partially aligned by market/application driver

    “Fabric” drivers: CPU, DSP/SPU, memory, AMS

    “Market” drivers: consumer mobile, office

  • Full alignment will be accomplished in ITRS 2006-7


Itrs inemi domain space
ITRS-iNEMI Domain Space

iNEMI

(emulators)

Market

requirements

ITRS

(Drivers)

Tech

requirements

Chip level

System level


Consumer portable system driver japan design twg
Consumer Portable System Driver(Japan Design TWG)

ES Level Methodology

Very large block reuse

Intelligent testbench

Large block reuse

Small block reuse

Tall thin engineer

IC implem. tools

In-house P&R

General

$10,000

$1,000

Selection

Productivity

Power

Manufac.

Interference

Reliability

$100

Design cost ($M)

$10

$1

Design

process

System

design

Logic/circuit

Physical D

Design

verification

Design

Test

DFM

(new)

1990

1996

2000

2002

2004

2010

1992

1994

1998

2006

2008

Mobile /Consumer SoC

PE-1

PE-2

PE-n

Main

Prc.

Memory

Updated productivity table  cost

Peripherals

Preserve consistency


Key driver trends
Key Driver Trends

  • Power consumption a first-class constraint

    Both for portable and non-portable applications

  • Highly parallel architectures

    Increasing number of “small” processing unit

  • System-On-Chip design techniques

    Assemble lots of pre-designed blocks


Overall requirements cont
--- Overall Requirements (cont.)

SOC Requirements




4 system drivers matrix alignment
4. System Drivers “Matrix” Alignment

Fabrics

HP

CP

MPU

2005

PE(DSP)

Size/weight ratio, battery life…

Power, interconnect speed…

Memory

AMS

Medical

Automotive

Office

Network

Defense

Portable

[Industrial]

Markets


4 system drivers matrix alignment1
4. System Drivers “Matrix” Alignment

Fabrics

MPU

2006

PE(DSP)

Memory

AMS

Medical

Automotive

Office

Network

Defense

Portable

[Industrial]

Markets


4 system drivers matrix alignment2
4. System Drivers “Matrix” Alignment

Fabrics

MPU

2007

PE(DSP)

Memory

AMS

Medical

Automotive

Office

Network

Defense

Portable

[Industrial]

Markets


Systems driver chapter future structure
Systems Driver Chapter Future Structure


Summary 2005 design system drivers
Summary  2005 Design & System Drivers

  • First Design For Manufacturability roadmap

    DFM roadmap tool

    Interface with other groups

  • First worldwide quantitative design technology roadmap

    System-level

    Logic/circuit/layout

    Verification

    DFT

    DFM

  • New SoC model captures emerging market driver

    Consumer driver

    improves alignment

    with other roadmaps

  • Emerging SoC fabric drivers updated

    Analog & MIxed-signal

    Embedded memory

In next 10 years, new drivers and technology limitations will require design technology overhaul at all abstraction levels