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ECT 358. Lecture 5 Introduction to Verilog 1. Although the tongue weighs very little, few people are able to hold it. Even so the tongue is a little member, and boasteth great things. Behold, how great a matter a little fire kindleth. James 3:5. Hardware Description Languages.

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ect 358

ECT 358

Lecture 5

Introduction to Verilog 1

although the tongue weighs very little few people are able to hold it
Although the tongue weighs very little, few people are able to hold it.

Even so the tongue is a little member, and boasteth great things. Behold, how great a matter a little fire kindleth.

James 3:5

hardware description languages
Hardware Description Languages
  • VHLIC HDL (VHDL)
  • Verilog HDL
  • AHDL
  • Parts
    • Text Based Description
    • Compiler
    • Simulator
verilog hdl
Verilog HDL
  • Top Down Design
  • Schematic Entry (Structural Description)
  • Truth Table
  • Boolean Entry (Functional Description)
  • Text Description (Behavioral Description)
  • Exported to Multiple Platforms and Designs
verilog module format
Verilog Module Format

moduledesign_name(port_list);

… // Declarations of ports

… //Functional details

endmodule

  • Syntax is similar to C.
  • Comments denoted by // or /* … */
  • Statements end in semi-colon.
  • Variable names are case sensitive.
  • White space is ignored (SPACE, TAB, new-line)
  • Functionality
  • Ports
  • Timing Constraints
  • No required order to port list
verilog structural primitives
Verilog Structural Primitives
  • The basic functional objects of logic gates
  • Outputs Followed by Inputs

Multiple Inputs – Single Outputs

and, nand, or, nor, xor, xnor

Multiple Outputs – Single Inputs

buf, not

Tri-State Multiple Outputs

bufif0, bufif1, notif0, notif1

verilog ports
Verilog Ports
  • Input
  • Output
  • Inout

module half_adder(a,b,sum,cout);

input a, b;

output sum, cout;

andg1(cout,a,b);

xorg2(sum,a,b);

endmodule

verilog wires

prim

A

F

B

Verilog Wires
  • Wire is an internal connection between primitives

module prim(A,B,F);

input A, B; output F; wire w;

not (w,B); and (F,A,w);

endmodule

wire

verilog nets
Verilog Nets
  • net_kind [msb:lsb ] net1,net2, ….net N;
  • net_kind is either wire or tri
  • msb and lsb are constant expressions that specify the range of the net
  • If no range is specified, range defaults to one bit
  • Examples

wire clk, a, b; // Three one-bit wire nets

wire [3:0] A, B; // Two four-bit wire nets

wire [range-1:0] busA //a parameterized net declaration

  • tri nets have same declaration form as wire nets
  • Use tri nets when multiple drivers drive a net
language rules
Language Rules
  • Case Sensitive My_input vs. my_input
  • Space Free
  • Upper and Lower case letters
  • Digits
  • Underscore
  • Dollar Sign
  • Variable cannot begin with Number or $
  • Reserved Keywords
  • Vectors indicate more than one wire sum[3:0]
other module functionality
Other Module Functionality
  • Register reg B[3:0]; //store values
  • Parameter parameter size=8;
  • Assign assign name = A && B;
  • Pullup pullup (out_y);
  • Pulldown pulldown (out_x);
assignments
Assignments
  • Blocking B = A;

C = B;

D = C; //A=B=C=D

  • Non-Blocking B <= A;

C <= B;

D <= C; //shift

radix s
Radix’s

Radix Description

d decimal

b binary

h hexadecimal

o octal

0 the number 0

10 the decimal number 10

′b10 the binary number 10

′h10 the hex number 10

4′ b100 the binary number 0100

8′b1000_0011 underscore _ can be inserted for readability

8′hfx equivalent to 8′b1111_xxxx

nested modules
Nested Modules

module halfadder (sum, c_out, a, b);

input a, b;

output sum, c_out;

xor (sum, a, b);

and (c_out, a, b);

endmodule

nested modules1
Nested Modules

module fulladder (sum, c_out, a, b, c_in);

input a, b, c_in;

output sum, c_out;

wire w1, w2, w3;

halfadder HA1(w1, w2, a, b);

halfadder HA2(sum, w3, c_in, w1);

or (c_out, w2, w3);

endmodule

truth table models
Truth Table Models

primitive my_table(y,x1,x2,x3);

output y;

input x1,x2,x3;

table

// x1 x2 x3 : y

0 0 0 : 1;

0 0 1 : 0;

0 1 0 : 1;

0 0 1 : 1;

1 0 0 : 1;

1 0 1 : 0;

1 1 ? : 1;

endtable

endprimitive

// ? Includes 0, 1, and x