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“Mismatch analysis for high speed, deep sub-micron blocks and simulation methodology” Task ID:906.001.

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**“Mismatch analysis for high speed, deep sub-micron blocks**and simulation methodology”Task ID:906.001 Task Leader :Alex Orailoglu, UC San DiegoStudents :Rasit Onur Topaloglu, UC San Diego, 2007Industrial Liaisons : Hosam Haggag, National Semiconductor Corp.Patrick Drennan, Freescale Semiconductor, Inc. Mien Li, Advanced Micro Devices, Inc.**Technical Thrust :Circuit designAnticipated Result :Mismatch**simulation and testing methods, with possible implementation in an EDA environmentTask Description :Provide measurement, simulation, test and verification methods for mismatch for deep-submicron technologies Task Deliverables :Report on developing a mismatch test methodology Report on developing level 1 sensitivity functions**Executive Summary**Accomplishments During the Past Year : Devised a test generation methodology to target mismatch Devised a general methodology to derive sensitivity functions for mismatch Devised Forward Discrete Probability Propagation Method for estimation of high level parameter probability distributionsFuture Direction : Implementation of these techniques at behavioral levels : will enable ability to use along with HDL, ex.Verilog-AMS**Executive Summary**Technology Transfer & Industrial Interactions : Monthly telephone communications to National Semiconductor on project progress Internship at National Semiconductor Publications :SRC Deliverable Reports : ( P007960 and P009498 )On Mismatch in the Deep Sub-micron Era : From Physics to Circuits , ASPDAC 2004**“Mismatch for Next Generation”Task ID: 1184.001**Task Leader :Alex Orailoglu, UC San DiegoStudents :Ayse K. Coskun, UC San Diego, 2008 Chengmo Yang, UC San Diego, 2008Industrial Liaisons : Hosam Haggag, National Semiconductor Corp.**Technical Thrust :Circuit designAnticipated Result :A**wafer-aware and design-to-avoid mismatch design flow for mixed-signal and RF circuits implemented in an EDA environment. Task Description :Provide mismatch-immune design and analysis methodologies including parasitics and passives Task Deliverables :Report on MINT modelsReport on mismatch verification and diagnosis, Nov04**Executive Summary**Technology Transfer & Industrial Interactions : Monthly telephone communications to National Semiconductor on project progress Future Direction : Discovery of mismatch integrated models and diagnosis Techniques to target mismatch**Outline**Test of Mismatch Motivation Mismatch Amplification Excitation Plots Mismatch Factor Test Generation Forward Discrete Probability Propagation Probability Discretization Theory Q, F, B, R Operators and r-domain Experimental Results Conclusions**GOALS**Low cost : measured in terms of speed and price of tester Separate design from test : to earn test engineers time Determinism : to provide pass and fail information Motivation for Testing • Functional testing is not the only method for digital circuits • While testing for stuck-at faults, other faults typically discovered also Find an analogous specialized test for mismatch**Bias, voltage, temperature and input used to amplify**mismatch • Aim is to differentiate circuit response from the nominal Mismatch Amplification Activate the defect, then propagate**Gain @100kHz vs. Widths of matched pair**• Dispersion from matched condition leads to appreciable reduction in observed parameter, ex. gain • Equal width variations in the pair =>negligible reduction Excitation Plots max-mismatch diagonal no-mismatch diagonal**A wider range of equal variations on no-mismatch diagonal =>**still negligible reduction Gain @100kHz vs. Widths of matched pair Deteriorating Effects of Mismatch no-mismatch diagonal**Fault-free responses are separated**• Vertical cuts are used in excitation plots for over-a-range plots Frequency response DC response Separation of Responses • Fault-free responses sit on no-mismatch diagonal**∆1**∆2 stepsize • 3-D response, when sampled, can be represented as a matrix • Mismatch Factor (MF) gives a degree of mismatch effect in circuit for some parameter, ex. tox on an analysis, ex. sampled AC gain Matrix representation of response: Mismatch Factor High MF => small mismatch causes appreciable impact**Sens. of AC gain to bias**Sens. of AC gain to VDD Other Observed Excitation Plots • MF still effective due to symmetric nature**Test Algorithm**• Mismatch (mm) pair, • physical parameter, • worst-case (V,T), obtain MF’s; select largest ones.**Input Choices**• Bias, voltage, temperature and input signal Analysis Choices • AC magnitude response : powerful for wide-band circuits • DC response : to be used for digital circuits • IDDQ : identified as being succesful for analog mismatch • Sensitivities of these : wrt. circuit biases and inputs Input and Analysis Choices Use circuit specs to constraint ranges: ex. AC or VDD range**AC100kHz**AC2GHZ .. DCVin=1.4V DCVin=1.5V IDDQ Analysis Types SAC100kHz SAC100kHz SAC2GHz SAC2GHz Vbias1 Vbias2 Vbias1 Vbias2 SAC100kHz SAC100kHz SAC2GHz SAC2GHz Vbias1 Vbias2 Vbias1 Vbias2 SIDDQ SIDDQ Vbias1 Vbias2 W, mm2 .. .. VFB, mmN • physical param. and mm pair, select highest MF in each row Test Generation Ex. : high coverage W, mm1 {VDD1, VDD2, T1, T2} Each entry excitation plot MF analysis type**AC100kHz**AC2GHZ .. DCVin=1.4V DCVin=1.5V IDDQ Analysis Types SAC100kHz SAC100kHz SAC2GHz SAC2GHz Vbias1 Vbias2 Vbias1 Vbias2 SAC100kHz SAC100kHz SAC2GHz SAC2GHz Vbias1 Vbias2 Vbias1 Vbias2 SIDDQ SIDDQ Vbias1 Vbias2 tox .. .. VFB • physical parameter, select highest MF in each row Test Generation Example : low cost W {VDD1, VDD2, T1, T2, mm1, mm2,..,mmN} Each entry excitation plot MF analysis type**AC2GHZ :Apply 1mV input AC at 3.3V, 300K, find AC gain**Test Set for Low Cost Example DCVin=1.4V : Apply 1.4V input DC 2.7V, 200K, find DC gain IDDQ :At 3.3V, 300K, find power supply current : Apply 1mV input AC at 2.7V, 200K; then change Vbias1 by 10% and repeat SAC2GHz Vbias1 : Apply 1mV input AC at 2.7V, 200K; then change Vbias2 by 10% and repeat SAC100kHz Vbias2 : At 2.7V, 200K, find power supply current; then change Vbias2 by 10% and repeat SIDDQ Vbias2 W • This test set targets the Width mismatch in the circuit If mismatch in Width parameter present, results differ appreciably**Test Set Size and Verification**• Reduction in number of test vectors intrinsic • Apply this test set before any functional test, as this test catches most hard faults • Test number can be reduced to analysis types*physical parameters • Test number is analysis types*physical parameters*mismatch pairs for increased fault coverage • As simulation based, verification also intrinsic**Outline**Test of Mismatch Motivation Mismatch Amplification Excitation Plots Mismatch Factor Test Generation Forward Discrete Probability Propagation Probability Discretization Theory Q, F, B, R Operators and r-domain Experimental Results Conclusions**GOALS**Determinism : a stochastic output using known formulas Algebraic tractability : enabling manual applicability Speed & Accuracy : be comparable or outperform Monte Carlo Motivation for Probability Propagation • Estimation of circuit parameters needed to examine effects of process variations • Gaussian assumption attributed to device parameters no longer accurate Find a novel propagation method**Shortcomings of Monte Carlo**• Non-determinism : Not manually applicable • Limited for certain distributions : Random number generators only provide certain distributions • Accuracy : May miss points that are less likely to occur due to random sampling; limited by the performance of random number generator**Probability Discretization Theory : QN Operator; p and r**domains spdf(X) or (X) • QN band-pass filter pdf(X) and divide into bins N in QN indicates number or bins pdf(X) p-domain r-domain Certain operators easy to apply in r-domain**Characterizing an spdf**• can write spdf(X) as : where : pi : probability for i’th impulse wi : value of i’th impulse spdf(X) or (X) r-domain**F Operator**spdf(X) or (X) Xi, Y : random variables pXs : Set of all samples s belonging to X • F operator implements a function over spdf’s • Function applied to individual impulses • Individual probabilities multiplied**Band-pass, Be, Operator**Margin-based Definition: • Eliminate samples having values out of range Error-based Definition: • Eliminate samples having probabilities least likely to occur**Impulses after F**Unite into one bin • Samples falling into the same bin congregated in one where : Resulting spdf(X) Re-bin, RN, Operator**Impulses after F, before B and R**The Necessity of Re-binning • Non-linear nature of functions cause accumulation in certain ranges Band-pass and re-bin operations needed after F operation**Error Analysis**Variance of quantization error: Distortion caused by representing samples in a bin by a single sample: mi : center or i’th bin Total distortion: • If quantizer uniform and small, quantization error random variable Q is uniformly distributed**Connectivity Graph Used in Experiments**• Connectivity Graphs can tie physical parameters to circuit parameters**Algorithm Implementing the F Operator**While each random variable has its spdf computed For each rv. which has all ancestor spdf’s computed For each sample in X1 For each sample in Xr Place an impulse with height p1,..,pr at x=f(v1,..,vr) Apply B and R algorithms to this rv.**Algorithm for the B and R Operators**Find maximum and minimum values wi within impulses Divide this range into M bins For each bin Place a quantizing impulse at the center of the bin with a height pi equal to the sum of all impulses within bin Find maximum probability, pi-max, of quantized impulses within bins Eliminate impulses within bins which have a quantized impulse with smaller probability than error-rate*pi-max Find new maximum and minimum values wi within impulses Divide this range into N bins For each bin Place an impulse at the center of the bin with height equal to sum of all impulses within bin**Q**Q NSUB T F B,R PHIf Q, F, B, R on a Connectivity Graph • Repeated until we get the high level distribution Useful for device characterization also**(X) for gm**Experimental Results (X) for Vth • Impulse representation for threshold voltage and transconductance are obtained through FDPP on the graph**Pdf of Vth**Pdf of ID Monte Carlo – FDPP Comparison solid : FDPP dotted : Monte Carlo • A close match is observed after interpolation**Monte Carlo – FDPP Comparison with a Low Sample Number**Pdf of F Pdf of F solid : FDPP,100 samples noisy : Monte Carlo, 1000 and 100000 samples respectively • Monte Carlo inaccurate for moderate number of samples • Indicates FDPP can be manually applied without major accuracy degradation**Custom pdf’s not possible without a custom random number**generator • Monte Carlo overestimates for one-to-many relationships as same sample is used Monte Carlo – FDPP Comparison one-to-many relationships and custom pdf’s P1 P2 P3 P4**Conclusions**• A specialized test selection mechanism for mismatch is introduced • Test of Mismatch is a deterministic, general and low-cost methodology • Forward Discrete Probability Propagation is introduced as an alternative to Monte Carlo based methods • FDPP should be preferred when low probability samples are important, algebraic intuition needed, custom pdf’s are present or one-to-many relationships are present

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