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XC16x architecture

XC16x architecture. Interrupt Response Time. Agenda. Advanced Interrupt System Definition of Interrupt Response Time Interrupt Flow Interrupt Response Time Interrupt PEC Transfer Conditions for Minimum Response Time Examples Spreadsheet Interrupt handling using Tasking Toolchain.

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XC16x architecture

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  1. XC16xarchitecture Interrupt Response Time

  2. Agenda • Advanced Interrupt System • Definition of Interrupt Response Time • Interrupt Flow • Interrupt Response Time • Interrupt • PEC Transfer • Conditions for Minimum Response Time • Examples • Spreadsheet • Interrupt handling using Tasking Toolchain

  3. Interrupt Response Time (Definition)

  4. Interrupt Flow • Peripheral / Fast External Interrupt • Interrupt Controller • CPU

  5. Peripherals / Fast External Intrrupts

  6. Interrupt Controller / CPU • Interrupt Handling

  7. Interrupt Controller / CPU • PEC Transfer

  8. Overview about Interrupt Response Time Can be influenced by the user

  9. Interrupt Response Time • The total Interrupt Response Time becomes shorter with: • Interrupt Jump Table Cache • The complete 24 bit address is supplied from a pair of dedicated register (FINTxCSP/FINTxADDE, instead of being fetched from the Interrupt Vector Table. • Starting an ISR from the Interrupt Vector Table • As the amount of words reserved for any Interrupt within the Vector Table can be set to 2,4,8,16 using VECSC. Therefor it is possible to place the most time-critical instructions from a ISR just there. The rest of the ISR can be placed in another program location. • Using Local Register Bank

  10. Interrupt entry point Jump Table Cache enable interrupt priority(12-15) segment address

  11. Register Banks (local / global) Register banks (local/global) can be selected for an interrupt level greater or equal 12, with group level 0..7

  12. Interrupt Response Time

  13. Interrupt Response Time (Optimum / Minimum Timing) • The optimal interrupt time ( 23 cpu clock cycle) based on following assumptions. • Code / Interrupt Vector Table / stack are located in dual ported internal program memory • PDBUS+ clock speed = CPU clock speed • no previous interrupt request is still proceeded • no stall / cancellation of the pipeline • Target address from Interrupt Vector Table holds a JMPS instruction to the start point of an ISR • Jump Table cache reduce interrupt response time to 19 cpu clock cycle • either local register bank or no context switch

  14. Example (Interrupt)

  15. Example (PEC)

  16. Interrupt Response Time (additional delays) • The following additional delays based on the assumption that PDBUS+ clock speed = CPU clock speed. • Interrupt controller busy (up to 9 cpu clock cycle) • Pipeline stalled / canceled (up to 4 cpu clock cycle) • Slower Memory (e.g. external, single ported memory) • Context switching of the global register bank (19 cpu clock cycle) • Switching to the local banks by changing directly the bit field BANK within the PSW register causes cancellation of the complete pipeline (6 cpu clock cycle + time to fetch next instruction).

  17. Calculation of Interrupt Response Time (Spreadsheet)

  18. Interrupt Response Time (Measurement)

  19. Tasking C-Compiler options / switches _stacksize (num) //specifies the userstack adjustment in byte _localbank (num) //local register bank switching (0,1,2,-1,-2) 0 = Global register bank -1 / -2 = local register bank1/2, BNKSEL0 should be used 1 / 2 = local register bank1/2, PSW is set in the ISR ( not recommended !) _cached //bypasses the interrupt vector table #pragma noframe //omit the whole interrupt frame, allows you to make your own interrupt frame

  20. Interrupt (None) interrupt (CC2_T7INT) void CC2_viTmr7(void) { #pragma asm BSET P1L.6 #pragma endasm }

  21. Interrupt (None) Fcpu = 40 MHz

  22. Interrupt (Interrupt Jump Table Cache) interrupt (CC2_T7INT) _cached void CC2_viTmr7(void) { #pragma asm BSET P1L.6 #pragma endasm } void CC2_vInit(void) {….. FINT0CSP = 0x8000 | (((unsigned long)&(CC2_viTmr7))>>16); FINT0ADDR = (unsigned int)&(CC2_viTmr7); }

  23. Interrupt (Interrupt Jump Table Cache) Fcpu = 40 MHz

  24. Interrupt (Fast Bank Switching) interrupt (CC2_T7INT) _localbank(-1) _stacksize(50) void CC2_viTmr7(void) { #pragma asm BSET P1L.6 #pragma endasm } void CC2_vInit(void) {….. BNKSEL0 = 0x0002; // Setlocal register bank 1 for Interr.level 12 / group 0 }

  25. Interrupt (Fast Bank Switching) Fcpu = 40 MHz

  26. Interrupt (Fast Bank Switching / Interrupt Jump Table Cache) interrupt (CC2_T7INT) _localbank(-1) _stacksize(50) _cached void CC2_viTmr7(void) { #pragma asm BSET P1L.6 #pragma endasm } void CC2_vInit(void) {….. FINT0CSP = 0x8000 | (((unsigned long)&(CC2_viTmr7))>>16); FINT0ADDR = (unsigned int)&(CC2_viTmr7); BNKSEL0 = 0x0002; // Setlocal register bank 1 for Interr.level 12 / group 0 }

  27. Interrupt (Fast Bank Switching / Interrupt Jump Table Cache) Fcpu = 40 MHz

  28. Interrupt (Fast Bank Switching / Interrupt Jump Table Cache) interrupt (CC2_T7INT) _localbank(-1) _stacksize(50) _cached void CC2_viTmr7(void) #pragma noframe // omit the whole interrupt frame { #pragma asm BSET P1L.6 #pragma endasm } void CC2_vInit(void) {….. FINT0CSP = 0x8000 | (((unsigned long)&(CC2_viTmr7))>>16); FINT0ADDR = (unsigned int)&(CC2_viTmr7); BNKSEL0 = 0x0002; // Setlocal register bank 1 for Interr.level 12 / group 0 }

  29. Interrupt (Fast Bank Switching / Interrupt Jump Table Cache) Fcpu = 40 MHz

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