ENG2410 Digital Design: Week #10 “Sequencing and Control”

1. ENG2410Digital Design: Week #10“Sequencing and Control” S. Areibi School of Engineering University of Guelph

2. Week #10 Topics • The Control Unit • Algorithmic State Machines • ASM Elements • Hardwired Control • One Flip-Flop Per State • Sequence Register and Decoder • VHDL Representation

3. Resources Chapter #8, Mano Sections • 8.1 The Control Unit • 8.2 Algorithmic State Machines • 8.3 ASM Examples • 8.4 Hardwired Control

4. CPU: Control Units

5. Parts of CPU • Datapath consists of: • Registers, Multiplexors, Adders, Subtractors and logic to perform operations on data (Comb Logic) • Control unit • Generates signals to control data-path • Accepts status signals to perform sequencing Control Data Path Switches

6. The Control Unit The binary information stored in a digital computer can be classified as either data or control information. • Data is manipulated in a data-path • To perform arithmetic, logic, shifting, and other data-processing tasks. • These operations are implemented with ALUs, registers, multiplexers, and busses. • The control unit • Provides signals that activate the various micro-operations in the data-path to perform the specified data processing tasks. • The control unit also determines the sequence in which the various actions are performed (i.e. when they are to be performed)

7. Control Unit Types • Two distinct classes: • Programmable • Non-programmable. • A programmable control unit has: • An external ROM or RAM array for storing instructions and control information • A program counter (PC) or other sequencing register with contents that points to the next instruction to be executed • Decision logic for determining thesequence of operations and logic to interpret the instructions • A non-programmable control unit (hardwired Control) does not fetch instructions from a memory but  just determines the operations to be performed and the sequence of those operations based only on inputs and status bits. • We will only cover non-programmable control unit

8. Algorithmic State Machines

9. Algorithmic State Machines (ASM) • The function of a state machine (or sequential circuit) can be represented by a state table or a state diagram. • What is wrong with state diagrams? • Gets messy as states grow • Decisions to move to different states is not present. • Solution? • A flowchart is a way of showing actions and control flow in an algorithm. • An Algorithmic State Machine (ASM) is simply a flowchart-like way to specify state diagrams for sequential logic and, optionally, actions performed in a datapath. • While flowcharts typically do not specify “time”, an ASM explicitly specifies a sequence of actions and their timing relationships.

10. State Box (a rectangle) Scalar Decision Box (a diamond) Vector Decision Box (a hexagon) Conditional Output Box (oval). The State Box is a rectangle, marked with the symbolic state name, containing register transfers and output signals activated when the control unit is in the state. The Scalar Decision Box is a diamond that describes the effects of a specific input condition on the control. It has one input path and two exit paths, one for TRUE (1) and one for FALSE (0). The Vector Decision Box is a hexagon that describes the effects of a specific n-bit (n > 2) vector of input conditions on the control. It has one input path and up to 2n exit paths, each corresponding to a binary vector value. The Conditional Output Box is an oval with entry from a decision block and outputs activated for the decision conditions being satisfied. ASM Primitives From Decision Box(es) (Register transfers (Input) START 00 10 R←0 Z, Q0 01

11. State Box A rectangle with: • The symbolic name for the state marked outside the upper left top • Containing register transfer operations and outputs activated within or while leaving the state • An optional state code, if assigned, outside the upper right top (Optional state code) (Symbolic Name) IDLE 0000 (Register transfers or outputs) R ← 0 RUN

12. Scalar Decision Box A diamond with: • One input path (entry point). • One input condition, placed in the center of the box, that is tested. • A TRUE exit path taken if the condition is true (logic 1). • A FALSE exit path taken if the condition is false (logic 0). (True Condition) (False Condition) (Input) 0 1 START

13. Vector Decision Box A hexagon with: • One Input Path (entry point). • A vector of inputconditions, placed in thecenter of the box, that istested. • Up to 2n output paths. The path taken has a binary vector value that matches the vector input condition (Binary Vector Values) (Binary Vector Values) (Vector of InputConditions) 00 10 11 01 Z, Q0

14. Conditional Output Box From Decision Box(es) • An oval with: • One input path from a decision box or decision boxes. • One output path • Register transfers or outputs that occur only if the conditional path to the box is taken. • Transfers and outputs in a state box are Moore type - dependent only on state • Transfers and outputs in a conditional output box are Mealy type - dependent on both state and inputs (Register transfers or outputs) R← 0 RUN

15. IDLE R← 0 AVAIL= 1 0 1 START PC ← 0 INIT Connecting Boxes Together • By connecting boxes together, we begin to see the power of expression. • What are the: • States? • Inputs? • Outputs? • Conditional Outputs? • Transfers? • Conditional Transfers?

16. Entry IDLE ASM BLOCK AVAIL START R← R + 1 R ← 0 Exit 0 1 Q0 Exit Exit MUL1 MUL0 ASM Blocks One state box along with all decision and conditional outputboxes connected to it is called an ASM Block. • The ASM Blockincludes all items on thepath from the currentstate to the same or otherstates.

17. State Diagram  ASM

18. From State Diagram to ASM Inputs S = 0 Z = 1 A B C S = 1 Z = 0

19. From State Diagram to ASM A 00 S = 0 Z = 1 0 1 S A B C B 01 S = 1 10 C Z = 0 0 1 Z

20. Example (1) • Find the ASM chart corresponding to the following description • There are two states A, B • If in state A and input X is `0’ then the next state is A • If in state A and input X is `1’ then the next state is B • If in state B and input Y is `1’ then the next state is B • If in state B and input Y is `0’ then the next state is A • Output Z is equal to `1’ while the circuit is in state B • Solution: • Total States  2 • Two Inputs  X, Y • One Output  Z

21. ASM for Example (1) A 0 1 X B Z = 1 1 0 Y

22. Example (2) • Find the Data Path and ASM for the following problem: • We first need to load two registers (R1, R2) with some value. • We will then need to add the two Registers (R1, R2) and save the result in Register R3. • All these operations should occur if a “start” Signal is activated. • Translation to Hardware: • We need to clear the registers first. • If the “start” signal is set to 0, I do nothing • Else If “start” signal is set to 1, load-1 R1, R2 with values • Next, enable R3 to be loaded (load-2)by the results of R1+R2 • Inputs/Outputs: • start is an input signal (Use a switch) • clear is an output signal generated and connected to R1, R2, R3 • load-1 is an output signal generated and connected to R1, R2 • load-2 is an output signal generated and connected to R3

23. Data Path? Switches Switches clear clear Register R1 Register R2 load-1 load-1 Adder Control Unit Implemented via ASM clear Register R3 load-2 • We need to clear the registers first. • If the “start” signal is set to 0, I do nothing • Else If the “start” signal is set to 1, load-1 R1, R2 with values • Next, enable R3 to be loaded (load-2)by the results of R1+R2

24. ASM Example 2 R1 0 R2 0 R3 0 A 00 0 1 S B R1 Val1 R2 Val2 01 10 C R3 R1+R2

25. Continue … ASM Example 2 CLR A 00 0 1 S B LD1 01 10 C LD2

26. Hardwired Control

27. Hardwired Control Designing the Control Unit: • One Flip-flop per StateA flip-flop is assigned to each of the states and at any time, only one of the flip flops contains a 1, with all the rest containing 0. • Sequence Register and DecoderUses a sequence register for the control states and a decoder to provide an output signal corresponding to each of the states.

28. One Flip Flop per State

29. I. One Flip-Flop per State • As the name implies the method uses one flip-flop per state and a simple set of transformation rules to implement the circuit. • The design starts with the ASM chart, • Then all you do is replace: • A State Box with a D flip-flop, • A Scalar Decision Box with a demultiplexer with 2 outputs, • A Vector Decision Box with a (partial) demultiplexer • Any Junction with an OR gate, and • Any Conditional Output with an AND gate • (for a Mealy Machine!!)

30. State Box Transformation Rules Each state box transforms to a D Flip-Flop • Entry point is connected to D FF input. • Exit point is connected to the D FF `Q’ output.

31. Scalar Decision Box Transformation Rules Each Decision box transforms to a Demultiplexer • Entry points are "Enable" inputs. • The Condition is the "Select" input. • Decoded Outputs are the Exit points.

32. (Binary Vector Values) (Binary Vector Values) (Vector of InputConditions) 00 10 01 X1, X0 Entry DEMUX Exit 0 D0 EN Exit 1 X1 D1 A1 Exit2 X0 A0 D2 Exit 3 D3 Vector Decision Box Transformation Rules Each vector decision box transforms to a Demultiplexer • Entry point is Enable inputs. • The Conditions are the Select inputs. • Demultiplexer Outputs are the Exit points. Entry

33. Junction Transformation Rules Where two or more entry points join, connect the entry variables to an OR gate • The Exit is the output of the OR gate

34. Conditional Output Box Rules • If each branch takes you to a different state or direction then use a Demux with two outputs. • Entry point is Enable input. • The Condition is the "Select" input. • Demux Outputs are the Exit points. • The Control OUTPUT is the same signal as the exit value. • If both branches take you to the same state then use a single AND gate instead of a Demux. The FF output will be directly connected to the next FF.

35. Implement using 1 Flip Flop Per State • Note: One FF is assigned to each of the states, and at any time, only one of the FFs contains a 1, with all the rest containing 0. • When a 1 is in the FF assigned to a particular state, the sequential circuit is in that same state. • The single 1 propagates from one FF to another under the control of decision logic A 00 0 1 S B 01 10 C 0 1 Z

36. One Flip Flop Per State 00 OR OR A 0 1 D S D 01 C C B 10 Z S DeMux DeMux C D 0 1 Z C

37. Conditional Outputs

38. Multiplier Example: ASM Chart IDLE MUL0 0 1 G 0 1 Q 0 Three states are employed using a Mealy output model: • IDLE - state in which: • input G is used as the condition for starting the multiplication, and • C, A, and P are initialized • MUL0 - state in which conditional addition is performed based on the value of Q0. • MUL1 - state in which: • right shift is performed to capture the partial product and position the next bit of the multiplier in Q0 • the terminal count of 0 for down counter P is used to sense completion or continuation of the multiply. C ← 0, A ← 0 P ← n – 1 A ← A + B, C ← C out MUL1 C ← 0, C || A || Q ← sr C || A || Q, 1 P ← P – 0 1 Z

39. Multiplier Example: ASM Chart IDLE MUL0 0 1 G 0 1 Q 0 C ← 0, A ← 0 P ← n – 1 A ← A + B, C ← C out MUL1 C ← 0, C || A || Q ← sr C || A || Q, 1 P ← P – 0 1 Z

40. Example - Sequencing Part of ASM IDLE 00 1 0 G MUL0 01 MUL1 10 0 1 Z

41. 2 DEMUX D EN 0 D A 1 0 Multiplier: One Flip-flop per State Design 4 5 START Initialize IDLE 1 D 4 5 C Clear _C 2 MUL0 Q 1 0 DEMUX Load D D EN 0 G A D C 0 1 MUL1 1 5 00 IDLE D Shift_dec Clock C 0 1 G 01 MUL0 Z 10 MUL1 0 1 Z

42. Sequence Register & Decoder

43. Sequence Register and Decoder This method uses a decoder and a set of flip flops (or a register) to implement the circuit. • The design starts with the ASM chart, • According to the number of states 2n, we will use n flip flops (log2 # state) • Construct State Table (directly from ASM) • Use an n-to-2n decoder  has 2n outputs

44. Implement  Sequence Register/Decoder A 00 0 1 S B 01 How many Flip Flops? 10 C Decoder Size? 0 1 Z

45. Implement  Sequence Register/Decoder Sequence Register Decoder D A 0 M0 C B 1 C M1 2 X D 3 C

46. State Table: 00 A 0 1 S 01 B 10 C 0 1 Z

47. Sequence Register and Decoder DM0 = A.S DM1 = B + C.Z’

48. Implement  Sequence Register/Decoder Decoder A D 0 B S A0 C 1 DM0 = A.S C DM1 = B + C.Z’ A1 2 D 3 C Z’

49. One FF per State vs. Seq/Reg/Dec • At first glance, it may seem that the one FF per state method would increase the cost of the system, since more flip-flops are used. • But the method offers some cost advantages that may not be apparent: • One advantage is the simplicity with which the logic can be designed – merely by inspection of the ASM chart or state diagram. • No state or excitation tables are needed if D flip-flops are employed. • This offers a savings in design effort, an increase in logic simplicity.

50. VHDL Implementation