1 / 24

Integration of entities in VHDL

Integration of entities in VHDL. Ing. Diego Barragán Guerrero http://www.matpic.com. Introduction . One of the strengths of VHDL is the ability to integrate "digital systems" that contain a large amount of electronic subsystems in order to minimize the size of the application.

sophie
Download Presentation

Integration of entities in VHDL

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Integration of entities in VHDL Ing. Diego Barragán Guerrero http://www.matpic.com

  2. Introduction. • One of the strengths of VHDL is the ability to integrate "digital systems" that contain a large amount of electronic subsystems in order to minimize the size of the application. • The integration of entities can be done by the individual design of each logic block, through several internal processes that can later be joined by a common program. • Another possibility is to observe and analyze the whole system comprehensively, evaluating its behavior only through its inputs and outputs..

  3. Programming of individual entities: Counter and Decoder

  4. Report for use of resources.

  5. Counter and decoder: Usingsignals.

  6. Keyboard, Encoder, Register, Decoder

  7. Keyboard, Encoder, Register, Decoder: TEST BENCH

  8. Keyboard, Encoder, Register, Decoder:Usingsignals.

  9. Keyboard, Encoder, Register, Decoder: TEST BENCH

  10. SIGNAL and VARIABLES • VHDL provides two objects for working with values of non-static data: signals and variables. • Constants and signals can be global (used in types of concurrent or sequential code). • A variable is local, only if used in sequential codes: processes. • SIGNAL • A “signal” used to pass values ​​input or output of a circuit, and between its internal units. • All ports of an entity are default signals. • Syntax: • SIGNAL name : type [range] [:= initial_value]; • Examples: • SIGNAL control: BIT := '0'; • SIGNAL count: INTEGER RANGE 0 TO 100; • SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0); • A signal can change its value by signal assignment statement, which is <= (eg: count<=35;) • A very important aspect of the signals, when used in a sequential section of code (process) is that its update is not immediate but occurs once run out of active processes.

  11. SIGNAL • Another aspect to consider in the signals, is that multiple assignment can be made ​​to a signal. The compiler may indicate a warning or not complete the syntax check, or inferring an erroneous circuit (considering only the last assignment, eg). • Contador de unos (1) • The code has multiple assignments to the same signal-temp-(temp <= 0, and temp <= temp + 1;). However, because the signal value is not updated immediately, both assignments are in conflict, since the value of first assignment is not fulfilled until the end of the process, so that an erroneous value is assigned in the second allocation.

  12. VARIABLES • Contrary to a signal or constant, a variable represents only local information. • It can only be used within a process (sequential code) and its value can not be transferred directly. • Its update is immediate, and the new value can be used immediately in the next line of code. • To declare a variable is used the following syntax : • VARIABLE name : type [range] [:= init_value]; • Examples: • VARIABLE control: BIT := '0'; • VARIABLE count: INTEGER RANGE 0 TO 100; • VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000"; • Because a variable can be used only in sequential code, should be placed in the declarative part of the process.

  13. VARIABLES • Counter of ones (1) • Because the variable is updated immediately, the initial value is set correctly and there is no conflict of multiple assignments.

  14. SIGNAL versus VARIABLE

  15. SIGNAL versus VARIABLE • Remember:Assigning to a variable is immediate, which is not the case of a signal. In general, the new value of a signal is only available at the end of the process. Usually, only one signal assignment is permitted within a process.. A common mistake is to forget to use signals that a certain amount of time is needed to update the signal. Thus, sel <= sel +1 code assignment will result in a more any value that was previously spread to sel, since the assignment sel <= 0 has not had time to update.

  16. SIGNAL versus VARIABLE • Recordar: la asignación a una variable es inmediata, lo que no es el caso de un señal. En general, el nuevo valor de una señal será solo disponible al finalizar del proceso. Por lo general, solo una asignación a señal es permitida dentro de un proceso. Cuando se usa variables, la asignación de variables es siempre inmediata.

  17. Asignación a SIGNAL • Recordar que un puerto es una señal por defecto. La asignación q<=d y qbar<=NOT q son ambas síncronas, de tal modo que sus nuevos valores serán disponibles solo al finalizar el proceso. Esto es un problema para qbar, debido a que el nuevo valor de q no se ha propagado todavía. Por lo tanto, qbar tomará el valor anterior a q, de tal modo que el valor de qbar estará un ciclo de reloj retardado. Resultando en un mal funcionamiento del circuito.

  18. Assignmentto SIGNAL • DFF In this example, the allocation is placed Qbar <= NOT q out of the process, so that it operates as a concurrent expression.

  19. Frequency divider: use of signals and variables. • Circuit which divides the clock frequency by 6.

  20. Frequency divider: use of signals and variables. • The generic statement is a very useful tool when several test values ​​required in an entity. The line GENERIC (N: INTEGER: = 5); define an integer variable N equal to 5, which determines the clock frequency division by 6 (N +1, due to counting from 0). Thus, to change the frequency division to another value, you only need to change N. Reset Asíncrono

  21. Number of Registers • A signal generates a “FF” whenever an assignment is made in the transition of another signal, that is, when a synchronous assignment occurs. • Such allocation, being synchronous, can only happen in a process (usually after the statement "IF signal'EVENT ..." or "WAIT UNTIL"). • A variable, on the other hand, will not necessarily create a “FF” if its value never leaves a process. • However, if the value is allotted to a variable in the transition of another signal, and this value is eventually passed to a signal (which leaves the process) will be inferred FF. • A variable also generates a register, when used before a value is assigned to it.

  22. Number of Registers • Examples: • In the process above, both as output2 output1 are stored (that is, an FF inferred) since both values ​​are assigned to the transition of another signal (clk).

  23. Number of Registers • Example2: • In the preceding example, only output1 is stored (output2 will make use of logic gates).

  24. Number of Registers: DFF withq and qbar • Both solutions work properly. The difference between them lies in the number required in each “FF” case.

More Related