implementation of parity bit generator checker n.
Skip this Video
Download Presentation
Implementation of parity bit generator/checker

Loading in 2 Seconds...

play fullscreen
1 / 14

Implementation of parity bit generator/checker - PowerPoint PPT Presentation

  • Uploaded on

Implementation of parity bit generator/checker. - Kavyashree Pilar. Project proposal. Implemen t ation of parity bit generator and checker circuit. Project d eliverables : Schematic Worst case timing analysis Power and thermal analysis

I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
Download Presentation

PowerPoint Slideshow about 'Implementation of parity bit generator/checker' - solana

Download Now An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
project proposal
Project proposal

Implementation of parity bit generator and checker circuit.

Project deliverables:


Worst case timing analysis

Power and thermal analysis

Hardware implementation and functionality verification.

  • Random data generator: Pseudo-Random noise generator circuit
  • Parity bit generator : Generates a logic high parity bit when odd number of data bits are on logic high state.
  • Channel : Represents noisy environment which can alter one or more data bits and the parity bit.
  • Parity checker: Generates a new parity bit using the data bits and compares it with the parity bit received with data.
components used
Components used

ICs used:

74AC164 : 8 bit shift register

74AC86 : Quad 2-input ExOR gate

PCB Board Specification:

Standard board : 10mils thick with copper routing layers on top and bottom.

termination resistors and bypass capacitors
Termination resistors and bypass capacitors

Trise_min= 3ns

F_knee = 166.66MHz

AC coupling capacitor value = 100pF

Length of rising edge(L) = 21.347”

L/4 = 5.3368”

Longest trace length ~ 5”

No termination required

timing analysis
Timing analysis
  • PNR data generator
    • tPLH of U1 = 12.5ns
    • tPLH of U2 = 10.8ns
    • Q5-Ex-or input = 0.7025
    • Ex-or output – B = 0.7025
    • Setup time for U1= 2.5ns
    • Minimum clock period = 27.205ns
    • Maximum operating frequency =36.76MHz
worst c ase p ower and thermal a nalysis
Worst Case Power and thermalAnalysis

U1: 74AC164

Each output drives 2 ExOR gate inputs

Q5 and Q6 drive one more ExOR gate

CPD= 150pF, Ci = 10pF, assume f = 36MHz


Pd = 234.3mW

θJA = 700C/W

Junction temperature = 51.4010 C

MTBF is very good – No cooling required.

power and thermal analysis continued
Power and thermal Analysis - Continued
  • All ExOR gates except U5 drive 4 ExOR inputs
    • Cpd = 57pF
    • Icc= 80uA
    • Ci = 10pF
    • Pd= 53.256mW
    • θJA = 700C/W
    • Junction temperature = 38.7280C
  • U5 drives 3 Ex-OR inputs:
    • Pd = 47.8115mW
    • Junction temperature = 38.34680C
next steps
Next steps
  • Hardware implementation
  • Functionality testing:
    • Verification of parity bit generation circuit
    • Verification of parity checker circuit

PCB design using OrCAD capture/CIS and PCB editor.

Issues faced and solutions:

ORCAD capture – schematic done V6.6 demo version can not be modified with V6.3.

Demo version can handle only upto 60 components.

The following command can be used on command prompt can be used when netlist generation via GUI fails:

C:\Cadence\SPB_16.3\tools\capture\pstswp -pst -d "<filename>.DSN" -n "allegro" -c "C:\Cadence\SPB_16.3\tools\capture\allegro.cfg"

learning continued
Learning - continued
  • CMOS design – analyze termination requirements before starting with the schematics.



CD54/74AC164, CD54/74ACT164 8-Bit Serial-In/Parallel-Out Shift Register - Texas Instruments

Thermal conductivity information

PCB Design :

“Capture CIS Tutorial” - EkaratLaohavaleeson

“Layout Editor Tutorial” - Jordan Bisasky