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AMD Advanced Packaging

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AMD Advanced Packaging

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AMD Advanced Packaging

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  1. 2 ADVANCED PACKAGING

  2. 6 Normalized Cost/yielded mm 90nm 65nm 45nm 32nm 22nm 4 14nm 10/7nm 2 - [1] [2] 45nm 32nm 28nm 20nm 14/16nm 7nm 5nm 2004 2007 2010 2013 2016 2019 Power of Top 100 Supercomputers 1000 Reticle Limit 100 MW Die Size (MM2) 10 MW 1 MW 100 KW 10 KW 100 [1] [3] 2006 2008 2009 2010 2012 Server CPU 2013 2014 GPU 2016 2017 2019 2020 2009 2019 [1] Naffziger, VLSI Short Course, 2020, [2] Cost per yielded mm2for a 250mm2die, [3] Data from top500.org 3 ADVANCED PACKAGING

  3. Die Size Increases over Time Reticle Limit 1000 100 Oct-06 Jul-09 Apr-12 Dec-14 Sep-17 Jun-20 Mar-23 Server CPU GPU ▪ ▪ ▪ ▪ 4 ADVANCED PACKAGING

  4. X X X 2X One Generation Later 2X X 1.5X X X ▪ ▪ ▪ 2X Device Functionality Costs > 2X Silicon Area 5 ADVANCED PACKAGING

  5. X X X X X X X X X X X X X X 6 ADVANCED PACKAGING

  6. (Hybrid 2D/2.5D & 3D) >10x BANDWIDTH DENSITY ▪ ▪ ▪ 7 ADVANCED PACKAGING

  7. ▪ ▪ ▪ 8 ADVANCED PACKAGING

  8. MCM INFO-R Micro Bump 3D Foveros-ODI Si Interposer + TSV INFO-L Foveros Intel: Omni-directional interconnect AMD Fiji GPU CoWoS-L Courtesy: TechSearch W2W stacking+ TSV+uBump WoW Intel: Foveros INFO-POP W2W F2F di-electric bonding+ TSV W2W F2F hybrid bonding w/o TSV EMIB TSMC: INFO-R/-L, CoWoS-L FoCoS Apple A10 on FO+POP Co-EMIB Courtesy: SystemPlus Consulting Sony: CMOS Image Sensors Samsung: HBM2 memory Courtesy: SystemPlus Consulting Courtesy: SystemPlus Consulting ASE: FoCoS Intel: EMIB and Co-EMIB Images courtesy: Intel, TSMC, Amkor, ASE from public material 9 ADVANCED PACKAGING

  9. + + + + 10 ADVANCED PACKAGING

  10. 11 ADVANCED PACKAGING

  11. 1000 100000 Linear Interconnect Density Area l Interconnect Density 10000 (Wires/mm/layer) 100 (Wires/mm2) 1000 10 100 1 10 12 ADVANCED PACKAGING

  12. 13 ADVANCED PACKAGING

  13. C4 and Micro Bump 3D illustrations are hypothetical 14 ADVANCED PACKAGING

  14. 15 ADVANCED PACKAGING

  15. 16 ADVANCED PACKAGING

  16. Based on AMD engineering internal analysis, May 2021 See endnotes. 17 ADVANCED PACKAGING

  17. 18 ADVANCED PACKAGING

  18. Based on AMD engineering internal analysis, May 2021 19 ADVANCED PACKAGING

  19. TSV Pitch DRAM on CPU Cores on Cores Die 2 Die 2 X carry TSV TSV CPU on CPU Cores on Uncore Die 1 Die 1 X Based on AMD engineering internal analysis, May 2021 20 ADVANCED PACKAGING

  20. 10000 Linear Interconnect Density Area l Interconnect Density 100000 1000 (Wires/mm/layer) (Wires/mm2) 100 1000 10 1 10 21 ADVANCED PACKAGING

  21. 22 ADVANCED PACKAGING

  22. 23 ADVANCED PACKAGING

  23. 24 ADVANCED PACKAGING

  24. 25 ADVANCED PACKAGING

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