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OUTPUT Pad and Driver. CLOCK DRIVER. Buffering. S = scaling or tapering factor CL = S N+1 Cg ……………… All inverters have identical delay of t o = delay of the first stage (load =Cd+Cg). 5. S. 4. 3. 0 1 2 3. Cd/Cg. Buffering.

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Presentation Transcript
buffering
Buffering

S = scaling or tapering factor

CL = SN+1 Cg ………………

All inverters have identical delay of

to = delay of the first stage (load =Cd+Cg)

buffering1

5

S

4

3

0 1 2 3

Cd/Cg

Buffering

If the diffusion capacitance Cd is neglected,

S = e = 2.7

output drivers
Output Drivers

Standard CMOS Driver

Open Drain/Source Driver: Single Transistors

Tri-state Driver

Bi-directional Circuit

tri state driver
Tri-state Driver

V

DD

En

Out

In

En

  • Tri-state or High impedance
  • Used to drive internal or external busses
  • Two inputs:
  • Data In and Enable
  • Various signal assertions
  • Two types:
  • C2MOS
  • CMOS with Control Logic

C2MOS

tri state driver1
Tri-state Driver

V

Control logic could be

modified to obtain

Inversion/non-inversion

Active low/high Enable

For large load, pre-drivers

are required

DD

En

PAD

Out

En

In

latch up trigger
Latch-up: Trigger
  • Factors which trigger latch-up
  • transmission line reflections or ringing
  • voltage drop on the VDD bus
  • “hot plug in” of unpowered circuit board
  • electrostatic discharge
  • sudden transient on power and ground busses
  • leakage current across the junction
  • radiation: x-ray, cosmic
protection circuitry principles
Protection Circuitry Principles

Avalanche

Punch Through

input protection
Input protection
  • Electrostatic discharge can take place through transfer of charges from the human body to the device.
  • Human body can carry up to 8000V.
  • Discharge can happen within hundreds of nanoseconds.
  • Critical field for SiO2 is about 7X106 V/cm.
  • For 0.5u CMOS process the gate oxide can withstand around 8V
  • Some protection technique is required with minimum impact on performance

1.5K

1M

Vesd

DUT

100pF

Human Body model

esd structures
ESD Structures

Basic technique is to include series resistance and two clamping diodes.

The resistance R is to limit the current and to slow down the high voltage transitions.

R could be polysilicon or diffusion resistance

Diffusion resistance could be part of the diode structure

Typical values of R: 500 to 1k

VDD

R

PAD

layout of esd structure
Layout of ESD Structure

PAD

n+

p+

Guard Ring

Guard Ring

p+

p+

n+

n+

This structure

uses transistors as

clamping diodes

layout of esd structure1
Layout of ESD Structure

VDD

PAD

n+

p+

Guard Ring

Guard Ring

p+

p+

n+

n+

GND

another esd structure
Another ESD Structure

VDD

R1

R2

PAD

Thick FOX

MOS Transistor

bi direct pad
Bi-direct PAD

V

DD

Pre-drivers

IN

ESD Protection

Input Buffer

PAD

Control

Logic

EN