SoC Design Flow. SoC Design Cycle. Concept Design Specification Engineering Specification Development Plan. Phase 1 – Specification. Spec. Sign-Off. ASIC Design, Full-Custom Design, DFT, Functional Verif. Plan Regression Analysis Pre-layout STA, Functional Review.
Phase 1 – Specification
DFT, Functional Verif. Plan
Phase 2 – Functional Design
Phase 3 – Physical Design
Post layout Sign-Off
Phase 4 – Prototype Fabrication
Prototype Acceptance Sign-Off
Phase 5 – Device Qualification
Release To Production Sign-Off
Phase 6 – Project Case Study
Conceptual idea about a functionality, that is thought through in the mind.
A functional representation of the idea, in the form of a flow chart or other text information. (specification).
A model that can be verified by a concept simulation. This may be written using a HDL or other high level languages like C.
Register Transfer Level, which is the architectural HDL that can be converted into a logical representation.
RTL mapped into an equivalent gate level netlist using a target library.
Physical specification that will help realize the device in silicon.
It is a method used to divide the design into smaller functional elements, so that a very complex design is split into simpler inner level modules.
What is the need for partitioning?
Managing ESD and Latch-up across digital and analog IOs
Decoupling Analog and digital power appropriately
Providing adequate physical guard rings
Suggesting process layer and design guidelines to handle Substrate Noise
Providing the right IO selectionHandling Mixed Signal Issues in Physical Design
During this task, the physical layout is checked against the functional gate-level schematic to ensure all intended connectivity has been maintained.
Antenna effects are long floating interconnects that act as temporary capacitors during the metalization process. Because a conducting path to ground does not exist at the time of metalization, a random discharge from the floating nodes can cause permanent gate oxidedamage
Antenna effects can be handled by inserting jumpers which minimizes the amount of charge collected by a floating node, by inserting buffers, or by inserting diodes near the input pins to provide a conduction path to ground
Req / Arch
IP & LIB
IP & LIB
IP & Mem
~Converged (5%)High-level Methodology
Validation Check List