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Program Modeling Concepts - Lesson-1: DFG, CDFG, SDFG, HSDFG and APEG Models

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Program Modeling Concepts - Lesson-1: DFG, CDFG, SDFG, HSDFG and APEG Models.

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Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Program Modeling Concepts -Lesson-1: DFG, CDFG, SDFG, HSDFG and APEG Models

Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

A software analysis is (i) a description of system requirement (ii) a provision of basic frame before the software is designed and (iii) a definition of set of requirements, using which designed software can be validated. It is done before software implementation.

Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Data flow graphs, abbreviated as DFGs and control data flow graphs, abbreviated as CDFGs are used for modeling the data paths and program flows of software during software analysis.

Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

1. Data Flow Graph (DFG) Model for Program AnalysisChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

- A data-flow means that a program flow and all program execution steps are determined specifically only by the data. A set of data-input generates a set of data-output and another set of input will generate another output.

A circle represents each process (set of program steps) in DFG. An arrow directed towards the circle represents the data input (or set of inputs) and an arrow originating from the circle represents a data output (or a set of outputs).Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

DFG Model is a model in whichChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

the designer predetermines the data inputs and designs the programming steps to generate the data output, with the steps represented by a circle. There are no control conditions in the steps

Example 1: Modeling of the steps to find the average value Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

A piece of code to find the average value A set of inputs will give one average and another set of inputs another. Program step for the average can be represented by a circle, the input by incoming arrow and output by outgoing arrow.

Example 2: DFG model of the steps for finding the 6th FIR SequenceChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Acrylic Data Flow Graph (ADFG)Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

When there is only one set of values of each of the inputs and only one set of values of the outputs for the given inputs, a DFG is also be known as an ADFG, (Acrylic Data Flow Graph).

APFG model of the steps for finding the 6th FIR SequenceChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Non Acrylic DataChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Examples of non-acrylic data input are as follows: (i) An event (ii) A status flag setting in a device and (iii) Input as per output condition of the previous process.

Data flow graph models help in a simple code design. A simple code design can be defined as that in which the program mostly breaks into DFGs. A DFG models a fundamental program element having an independent path. Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

A DFG gives that unit of a system, which has no control conditions and thus a single path for the program flow. Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

A unit gives the program context and helps in analyzing a program in terms of complexity. A more complex program would have a lower number of DFG processes than a simple program. Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

2. Control Data Flow Graph (CDFG) Model for Program AnalysisChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

- A control flow means that specifically only theprogramdetermines all program execution steps and the flow of a program. The software designer programs and predetermines these steps.

The steps may have loops or condition statements in-between. Data that is input generate the data output after a control data-flow as per the controlling conditions. Output(s) and paths taken after the steps depends on the control statements for various decisions in a process. Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

In the CDFG model, there is a diagram, which graphically represents the conditions and the program flow along a condition dependent path. The CDFG diagram also represents the effect of events among the processes and shows which processes are activated on each specific event. Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Here, a variable value changing above a limit or below a limit or falling within a range is also like an event that activates a certain processChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Example 1: Modeling of the steps (a) Data inputs and Controlling input (decision) nodes shown by test boxes in a CDFG for an FIR filter with ten inputs and 10 coefficients

A CDFG ModelChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Example 2: Controlling inputconditions marked for Port A interrupt service in In_A_Out_B programs in Examples 4.1 and 4.2. [Instead of box, a condition is marked at the start of an arc]

Port A Interrupt Service Conditions in CDFG ModelChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

3. Synchronous Data Flow Graph (SDFG) ModelChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

DFG assumptions: A set of the outputs from a circle showing a set of programming steps will be simultaneously available as the inputs to the next circle (next set of programming steps).

DFG assumes that at each circle the computations take same time for each output and there is therefore no delay in any of the inputs from previous stage.Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Modeling of the delay in getting an input (s) before the all or part of computation(s) fire at a circle in the DFG.Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

- Modeling of number of outputs from the program steps at a circle and modeling the number of inputs.

An SDFG models as a DFG does but it shows the delay(s) [expected due to a previous process may not yet have been completed] as well as shows the number of inputs and outputs.Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

An arc (directed arrow) represents a buffer in physical memory. The arc can contain one or more initial tokens with the delays. A token till received at vertex (shown by a circle) does not fire the computations (actors) at a vertex (circle). [Token means output on finishing certain computation or an asynchronous event.]Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

An initial token may also represent a delay that is shown by a dot on the edges of an SDFG Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

- If there are more than one initial token, the number of initial tokens are mentioned on the dot.

Example 1: SDFG model of computations (actors) at the vertices shown by circles) and memory buffer by arcs in a directed graph between X and Y. The delay in the inputs is shown by dot. Number of inputs and outputs also marked.

Memory buffer shown by arc in a directed graph between X and Y in SDFG Model; Dot shows delayChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Example 2: SDFG model: Actors (Vertices shown by circles) and arcs in a directed graph between X and Y. The outputs are a, b and c and inputs are a, c, i and j. The i is with a delay (dot).

SDFG model actors and arcs in a directed graph between X and Y.Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

4. Homogenous Synchronous Data Flow Graph (HSDFG) ModelChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

When there is only one token at the input, and one at the output, an SDFG is called a homogenous SDFG (HSDFG).

For example, if the outputs from vertex X' (a set of computations) is a and input to Y' (another set of computations) is also a, the SDFG is equivalent to an HSDFG. An SDFG can always be unfold into the HSDFG(s)Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Example of an SDF graph unfolded into one or more HSDFGs: Two vertices can be connected by two or more edges in the HSDF graph. Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

- An HSDF graph will thus naturally have more vertices and edges than an SDFG because only one token is permitted at a vertex.

HSDFG model of actors (Vertices shown by circles) and memory buffer after unfolding an SDFG in which a vertex gives (a, b, c) outputsChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

HSDFG model actors after unfolding an SDFG Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Acrylic Precedence Expansion Graph (APEG) ModelChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

Acrylic precedence is a precedence of vertices in a directed graph such that there are no delays at the arcs. If initial tokens (delays) are taken off from an HSDF graph, an acrylic precedence expansion graph (APEG) is obtained.

Importance of an APEG: An APEG not only has along an arc, starting inputs identical to the output from a previous vertex, but also no delaying tokens. Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

An initial token does not represent delay and there is no dot on the edges of an SDFG or HSDFGChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

APEG model of actors (Vertices shown by circles) and memory buffer after unfolding an SDFG after removing the delayed path(s) Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

APEG model of computations on a processor PA Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

SummaryChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

We learntChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

- (i) A programming task is simplified by representing the code for its each process by a circle, using the data input from an incoming arrow(s) and generating data output along an outgoing arrow(s).

(ii) DFG models a process or set of processes with the single data-in and single data- out points, the process is represented by a circle(s) ad there are no control conditions within the process.Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

(iii) Software implementation becomes simplified when using the specifications of conditions and decision nodes in CDFGs, which represent the controlled decisions at nodes, and the program paths (DFGs) that are traversed consequently from nodes after decisions.Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

We learntChapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

- (iv) ADFG, SDFG, HSDFG, APEG models, that are derived from the DFG model.

End of Lesson 1 of Chapter 6Chapter-6 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

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