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FlexiForm Microprocessor Modeling: A Tool for Retargetable Simulation

This study presents a flexible and formal microprocessor modeling approach for retargetable simulation, focusing on the efficient, expressive, declarative, and productive aspects of the Operation State Machine (OSM) formalism. It discusses the modeling of microprocessors using OSM, token management, language constructs, control behaviors, and a case study with StrongArm and PowerPC processors.

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FlexiForm Microprocessor Modeling: A Tool for Retargetable Simulation

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  1. Flexible and Formal Modeling of Microprocessors with Application toRetargetable Simulation • Presented By : Min Chen Authors: Wei Qin Sharad Malik

  2. Objective • Modeling environments based on precise semantics that can be used for rapid generation of detailed processor simulators • Microprocessor simulation • Instruction set simulators (ISS) • Emulate the functionality of programs • Micro-architecture simulators • Provide performance metrics, functionality of programs

  3. Four important characteristics • Efficient • Expressive • Declarative • Productive Operation State Machine (OSM) Formalism A flexible and formal microprocessor model that is properly balanced in terms of the above characteristics.

  4. Related Work • Operation-centric : nML, ISDL, EXPRESSION • Hardware-centric : MIMOLA, HASE, Asim, Liberty • Special Attempts: LISA, UPFAST, BUILDABONG

  5. Operation State Machine Model • OSM • Token and Token Managers • Language • Director

  6. Language – Four primitive transaction • Allocate • OSM Request token from a manager • Inquire • Inquire about the resource • Release • Request to return a token • Discard • Discard a token

  7. Director • Ensures that the behavior of the model is deterministic. • Scheduling rules: • State transition occurs at most once for each OSM at each control step. • State transition occurs as soon as an outgoing edge has satisfied condition. • State transition along a higher priority edge is preferred.

  8. Modeling Microprocessors • During the interval between two control steps, the hardware modules communicate with one another and exchange information with their TMIs. • TMIs for the 5 pipeline stages. • Register file contains a TMI mr

  9. Common Control Behaviors • Structure Hazard • Data Hazard • Variable latency • Control Hazard

  10. Case Study • StrongArm • Average speed 650k cycles/sec vs. SimpleScalar tool-set at 550k cycles/sec • PowerPC • 250k cycles/sec on a P-III 1.1GHz desktop, 4 times that of SystemC model

  11. Conclusion • Efficient • Compared with model purely in hardware domain • Expressive • Suitable for a wide range of architectures • Declarative • Can be automated through the use of descrition languages • Productive • Clean separation of peration/hardware layer

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