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Scalable Pattern Matching for High Speed Networks

Explore scalable pattern matching techniques for high-speed networks using FPGA technology. Learn about three methods - brute-force, deterministic finite automata, and non-deterministic finite automata - along with distributed comparators and a character decoder pattern-matching module. Discover a parallel NFA circuit for the pattern "abcde" and performance comparisons with previous work. This comprehensive study provides insights into optimizing throughput and capacity trade-offs in network pattern matching.

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Scalable Pattern Matching for High Speed Networks

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  1. Scalable Pattern Matching for High Speed Networks Authors: Christopher R.Clark and David E. Schemmel Publisher: Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines(FCCM) Present: Kia-Tso Chang Date: November 1 2007

  2. Three designed method on FPGA • 1. brute-force, • 2. deterministic finite automata (DFA) • 3. non-deterministic finite automata (NFA).

  3. Distributed comparators and Character Decoder

  4. Pattern-matching module using multi-character decoder

  5. Four-character parallel NFAcircuit for the pattern “abcde”

  6. Upper bound of per matcher

  7. Upper bound of per matcher • Each FPGA logic element (LE) can implement up to a four-input logic gate and a flip-flop,

  8. Upper bound of per matcher

  9. Upper bound of per matcher

  10. Experiment result

  11. Experiment result

  12. Throughput and capacity trade-off summary

  13. Throughput and capacity trade-off summary

  14. Performance comparison with previous work

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