ECE3801 Note Sheet

1. ECE3801 Note Sheet SR Latch Q Q S D Q1 Q1 R C Edge Trig. D Flip-Flop Q D Q1 > CLK J Q > CLK Q1 K Boolean Algebra, Etc. D Latch Edge Trig. JK Flip-Flop State Machine Types Sequencer: Current State  Output Current State  Next State Moore Machine: Current State  Output Current State, Input  Next State Mealy Machine: Current State, Input  Output Current State, Input  Next State Transition Key  State Machine DESIGN Steps 1) Draw state transition diagram. 2) State minimization; Number of flip-flops; Unused states. 3) State assignment and transition table. 4) Logic synthesis. 5) Implement. State Machine ANALYSIS Steps 1) Identify next state, output logic blocks, machine type. 2) Write output, next state equations. 3) Construct state transition table. 4) Construct state transition diagram.

2. VHDL for Comb. Logic State Machine Timing (D Flip-Flops) 1) AND 2) AND 3) ENTITY Format ENTITY Ename IS PORT(name1, name2 : Mode Type; name3, … : Mode Type); END Ename; IEEE 1164 Library LIBRARY ieee; USE ieee.std_logic_1164.ALL; • VHDL File Layout: • Library Definitions • ENTITY Declaration • ARCHITECTURE ARCHITECTURE Statements Boolean: AND, OR, NAND, NOR, XOR, XNOR, NOT ARCHITECTURE Format ARCHITECTURE Aname OF Ename IS {Optional Definitions} BEGIN {Architecture Body} END Aname; Selective Signal Assignment: WITH a SELECT y <= “010” WHEN “00”| “01”, “101” WHEN OTHERS; WHEN-ELSE: y<= “001” when a = “00” else “010” when a = “01” OR a = “10” else “100”; Quine-McCluskey Minimization 1) Find all prime implicants using code word lists. 2) Minimize using cover table, etc. Exhaustive State Minimization 1) Create simplified state transition table (i.e., state assignments omitted). 2) Eliminate redundant states satisfying “sufficient” conditions (i.e., same outputs, next states for each input). 3) Construct implication chart: a) One box per pair of states. b) Eliminate state pairs with different output functions. c) Write implied next state equivalences. d) Eliminate implied equivalency conflicts. e) Read results. Synchronization Failure tr = metastable resolution time (usually tCLK – tns – tsetup), f = flip-flop clock frequency, a = frequency of asynchronous input changes, t, To = constants. AC Characteristics of Simple Gates in ns (TA=25oC) [From: Motorola Fast and LS TTL Data (DL121/D, Rev 5)]