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  1. BOOTH MULTIPLIER Under the Guidance of Mrs.M.Rupa & Mr. R.Srikanth By U.Srinivas 08B81D5714

  2. Introduction : • Multiplication is more complicated than addition, being implemented by shifting as well as addition. • Multiplication: Partial products generation + accumulation • Because of the partial products involved in most multiplication algorithms, more time and more circuit area is required to compute, allocate, and sum the partial products to obtain the multiplication result.

  3. A Booth multiplier is a hardware multiplier that performs multiplication of two signed (two's complement) binary numbers (integers) • Booth algorithm, which encodes a binary number one bit-pair at a time to the signed-digit set S = {-2, —1,0,1,2},is often used to encode one of the multiplier inputs to reduce the number of partial products that need to be added.

  4. Multiplication Example : Example: 12x5 Multiplicand: 1 1 0 0 12Multiplier: 0 1 0 1 5 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 60 4 partial products

  5. Multiply Signed Numbers : 0 1 0 1 +5x 0 0 1 1 +3 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 +15 1 0 1 1 -5x 0 0 1 1 +3 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 -15

  6. Multiply Signed Numbers (cont..) 1 0 1 1 -5x 1 1 0 1 -3 1 0 1 1 -5x 0 0 1 1 +3 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 -15 0 0 0 1 1 1 1 +15

  7. Booth Multiplication: -1 -2 0 0 0 1 1 0 1 13 1 1 1 0 1 0 -6 1 11 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 i+1 i i-1 add 0 0 0 0*M 0 0 1 1*M 0 1 0 1*M 0 1 1 2*M 1 0 0 –2*M 1 0 1 –1*M 1 1 0 –1*M 1 1 1 0*M 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0

  8. Booth Recoding Table : i+1 i i-1 add 0 0 0 0*M 0 0 1 1*M 0 1 0 1*M 0 1 1 2*M 1 0 0 –2*M 1 0 1 –1*M 1 1 0 –1*M 1 1 1 0*M

  9. 8-Bit Simple Multiplication:

  10. 8-Bit Booth2 Multiplication :

  11. 8-Bit Booth 2 Example:

  12. Block Diagram of Booth Multiplier : Y X BOOTH DECODER PARTIAL PRODUCT BOOTH DECODER PARTIAL PRODUCT ADDER BOOTH DECODER PARTIALPRODUCT ADDER BOOTH DECODER PARTIAL PRODUCT ADDER PRODUCT OUTPUT : P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0]

  13. Project Floor Plan :

  14. 8 Bit Partial Product Selector Logic:

  15. Advantages and Disadvantages: Depends on the Architecture Potential advantage: might reduce the no. of 1’s in multiplier In the multipliers that we have seen so far: Doesn’t save in speed-still have to wait for the critical path, e.g., the shift-add delay in sequential multiplier Increases area: Recoding circuitry AND subtraction

  16. Summary : The Booth 2 algorithm is the fastest, but is also quite power and area hungry. The fastest version of this algorithm is as fast as the Booth 2 algorithm, but provides modest decreases in both Power and Area . Input delay variations are important when designing summation networks, if the highest possible performance is desired.

  17. Conclusion : The primary objective of this thesis has been to present a new type of partial product generation algorithm. i.e., Booth to reduce the implementation and to show through simulation and design. This algorithm is competitive with other more commonly used algorithms. which used for high performance implementations. Modest improvements in area and power over more conventional algorithms have been shown using this algorithm.

  18. Conclusion (contd..) Secondarily, this thesis has shown that algorithms based upon the Booth partial product method are distinctly superior in power and area when compared to non-Booth encoded methods. This result must be used carefully if applied to other technologies, since different trade-offs may apply. The summation network and partial product generation logic consume most of the power and area of a multiplier. So there may be more opportunities for improving multipliers by optimizing summation networks to try to minimize these factors. Reducing the number of partial products and creating efficient ways of driving the long wires needed in controlling and providing multiples to the partial product generators are areas where further work may prove fruitful.

  19. Bibilography : • [1] G. Bewick, P. Song, G De Micheli, and M. J. Flynn. Approaching a Nanosecond : A 32 Bit Adder. In Proceedings of the 1988 IEEE International Conference on Computer Design, pages 221–226, 1988. • [2] Gary Bewick and Michael J. Flynn. Binary Multiplication Using Partially Redundant Multiples. Technical Report CSL-TR-92-528, Stanford University, June 1992. • [3] A. D. Booth. A Signed Binary Multiplication Technique. Quarterly Journal of Mechanics and Applied Mathematics, 4(2):236–240, June 1951. • [4] IEEE Standard for Binary Floating-Point Arithmetic, 1985. ANSI/ IEEEStd 754-1985. • [5] Norman P. Jouppi. Multi Titan Floating Point Unit. In Multi Titan: Four Architecture Papers. Digital Western Research Laboratory, April 1988. • [6] H. Ling. High-Speed Binary Adder. IBM Journal of Research and Development, 25(2 and 3):156–166,May 1981. • [7] O. L. MacSorley. High-Speed Arithmetic in Binary Computers. Proceedings of the IRE, 49(1):67–91, Jan 1961. • [8] Multiplier with 0:5m CMOS Technology. In 1990 Symposium on VLSI Circuits, pages 125–126, 1990.

  20. BOOTH DECODER :

  21. Test Bench :

  22. Carry Look Ahead Generator :

  23. Test Bench :

  24. Partial Product Term :

  25. Test Bench :