Diagnosis and Correction of Logic Design Errors in Circuits

1. Diagnosis and Correction of Logic Design Errors in Circuits Student: Yu-Lin Hsiao Advisor: Chun-Yao Wang 2006.9.1 Department of Computer Science National Tsing Hua University, Taiwan

2. Outline • Introduction • Previous work • Problem description • Our method • Future work

3. Introduction • Design errors often occur when designers optimize the circuit for area or timing manually. • Error Diagnosis And Correction(EDAC) ‧fix the incorrect implementation ‧Engineering Change (EC) problem

4. Introduction (Cont’d) • Error diagnosis is performed to locate the potential error sources. • Based on the diagnosis results, error correction can be performed to fix errors.

5. Introduction (Cont’d) • Challenge : ‧solution space : (# ckt lines)(# errors) ‧errors increase : difficult to get a satisfied solution. ‧EDAC on sequential circuits remains a difficult problem.

6. Outline • Introduction • Previous work • Problem description • Our method • Future work

7. Previous work (1/7) • Simulation-based approach ‧By simulating input vectors, try to guess the error locations, and the potential error region can be pruned gradually. ‧Three heuristic methods: ─ Cone Intersection, ─ Sensitization-based Filter, 　 ─ Back Propagation.

8. Previous work (2/7) • Cone intersection x1 I1 incorrect x2 x5 I2 incorrect x3 x4 Drawback: solution space is still large and only used for single error

9. Previous work (3/7) • Sensitization-based Filter 1 0 x1 1 I1 incorrect x2 1 1 0 1 x5 1 0 I2 1 0 incorrect x3 1 0 1 1 x4 Drawback: have to recompute the whole circuit

10. Previous work (4/7) • Back Propagation 0 1 x1 1 I1 incorrect x2 1 1 x5 0 I2 1 1 incorrect x3 0 1 1 x4 Drawback: have to trace to PIs

11. Previous work (5/7) • Symbolic approach ‧It rely on OBDD to formulate the necessary and sufficient condition of a single fix signal. ‧More accurate than simulation-based approach ‧Give more information about correction. ‧May cause memory explosion and timing-consumed.

12. Previous work (6/7) New function I1 I1 f f’ I2 I2 … … In In inputs inputs Ii(X,f’) : the function of output Ii treating f’ as a pseudo PI Si : the function of output Ii in the specification If E(x,f)=0, there should exist a new function at f

13. Previous work (7/7) f1new f2new I1 I1 f1 I2 I2 f2 …… …… inputs inputs In In If E(x,f1,f2)=0, there should exist two new functions at f1,f2

14. Outline • Introduction • Previous work • Problem description • Our method • Future work

15. Problem Description • Given two netlists C_org and C_opt C_org is the original circuit C_opt is the timing/area optimal circuit • If there exists at least one output which is in both circuits are not equivalent, the C_opt is considered as having design errors.

16. Problem Description (Cont’d) • Assume there are few design errors in the C_opt, and 6 error types are included. • Both circuits consist of simple gates : AND, OR, NOT

17. Error models (for 2-inputs gate) Simple Design Error Incorrect Correct (1) Extra inverter (2) Missing inverter (3) Simple Gate Replacement

18. Error models (for 2-inputs gate) (Cont’d) Simple Design Error Incorrect Correct G1 (4) Incorrectly placed gate input G1 G2 G2 G3 G3 G1 G1 (5) Extra Gate complex case G3 G2 G2 G1 G1 (6) Missing Gate complex case G3 G2 G2

19. Outline • Introduction • Previous work • Problem description • Our method • Future work

20. Basic idea • Use single error correction scheme to correct multiple errors in the implementation iteratively. • Guarantee the error bits will decline in each iteration. • Modify the incorrect circuit as little as possible.

21. Basic idea (Cont’d) • Cut and Paste - cut a suspected error part of the circuit. How to choose a proper cut point to paste a new sub- circuits? - paste a new sub-circuits we create to cut point and throw away useless sub-circuits we cut . How to build a proper new circuit? • Traverse each level of the circuit from POs to PIs and perform cut and paste procedures until all error bits are fixed.

22. Lemma(1) a b b a 1 0 … … 1 0 The change of input a’s value can be propagated out only when the others’ values are all 0. The change of input b’s value can be propagated out only when the others’ values are all 1.

23. Example Use Lemma(1) to show which bits in a line can be propagated out Error bits : 7,8 {8,7,4,3} {8,7,6,5,4,3} 10101010 01010101 10001000 {8,7,6,5,4,2} 00110011 11001100 10001011 10001111 00110011 00000011 00001111 {7,6,5,3,2,1} {4,3,2,1} 01001111 01010101 00000101 00001111 {7,6,5,3} {7,5,3,1}

24. Definition (1) • If bits propagated set has all error bits, this line is called full correctable. • If bits propagated set has some of the error bits, this line is called strongpartial correctable. • If bits propagated set has no any of error bit, this line is called weak partial correctable.

25. Find cut • For every gate inputs, if there is a full correctable line, choose this line to cut. • If not, choose a strongpartial correctable line to cut. (means this circuit needs to be rectified many times) • If there is no full or strong partial correctable line, choose a weak partial correctable line.

26. Reuse the sub-circuit If g or h is a sub-function of f h Append the new function f g f g , h If f is a sub-function of g or h Append the new function f g , h

27. Create new function (1/6) • Split new function into two groups, one for don’t care set, the other for not don’t care set. • Example 01xx1xxx: Don’t care Not Don’t care

28. Create new function (2/6) If there is a reusable function We can set dominated bits as don’t care. 01xx1xxx 01001xxx 10101010 10001000 01001x1x 01001111 11001100 10001011 10001111 00000011 Bits value=0 in this line can dominate those in the new function. 01001111 00000101 Bits value=1 in this line can dominate those in the new function.

29. Create new function (3/6) New function • Gate type is OR 1 OR 3 : 2 AND 3’ : 1 3 Wanted function 2

30. Create new function (4/6) New function • Gate type is AND 1 OR 3’ : 2 AND 3 : 3 1 Wanted function 2

31. Create new function (5/6) If there is no reusable function Error bits: 8,6,5,4,2,1 01000100 01001111 {7,5,4,3,2,1} 01110100 01001111 Create function according to its propagated set 00110000 11110100 {8,4,2,1} 10100000 0x00xxxx

32. Create new function (6/6) If error bits can propagate out from two sources, set them as don’t care. If non-erroneous bits can’t propagate out, set them as don’t care 3:progate bits array {7,5,4,3,2,1} 01110100 5: error bits array 11110100 1 {8,4,2,1} 10100000 4:progate bits array Wanted function 2

33. Example (1/7) Error bits{1,2,4,5,6,8,9,10,12,17~32} c e a b 1010101010101111 1010101010101010 d Correct implementation c e a b 0111011101111111 0101010101010101 d Incorrect implementation

34. Example (2/7) Error bits{1,2,4,5,6,8,9,10,12,17~32} l c e m a b New function: 1010101010101111 1010101010101010 1. l, m both are not reusable function 2. Move to next level

35. Example (3/7) Error bits{1,2,4,5,6,8,9,10,12,17~32} {1,5,9,17~32} l c e a m b {1,3,5,7,9,11,13,15,17,19,21,23,25,27,31} • l, m are both partial correctable cut. Choose l first. New function: x0x0x0x0x0x0xxxx x0x0x0x0x0x0x0x0 2. Create new function. 3. l’ is a reusable function. Connect it and exam . 4. {1,5,9,17~32} are fixed. Correct it!! (add INV) 5. Error bits decline!! 1st iteration done !!

36. Example (4/7) Error bits{2,4,6,8,10,12} l c e a m b j 1111111111111111 1010101010101010 • e and j are both reusable. Connect it and exam 2. No error bits are fixed. 3. Move to next level.

37. Example (5/7) Error bits{2,4,6,8,10,12} l c e a m b n j 1111111111111111 1010101010101010 k • e ,j are both full correctable cut. Choose non-PI line j. 2. k, n are both reusable. Connect it and exam. 3. {2,4,6,8} are fixed. Correct it. (change OR to AND) 4. Error bits decline!! 2nd iteration done !!

38. Example (6/7) Error bits{10,12} l c e a m b n j 1010101011111111 1010101010101010 k 1. Line c equals new function 2. {10,12} are fixed, correct it !! (remove OR gate and n’s branch, connect c only.) 3. Error bits decline to 0!! 3rd iteration done!!

39. Example (7/7) e c a m b n j 1010101010101111 1010101010101010 k Complete correction!!

40. Algorithm flow Specification Implementation Search circuit’s lines or append minterms to fix remaining error bits Probability checking Y Correction done Y All outputs eq? Are all inputs PIs? N N N Error bits decline? Find cuts Move to the next level Y Create new function N Connect them Is there a reusable function? Y

41. Circuit similarity matrix • Function Equivalent Pairs (FEP) How many equivalent functions between original correct ckt and modified correct ckt. • Node Number Similarity (NNS) The relation of node numbers original correct ckt and modified correct ckt have.

42. Circuit similarity matrix A Number of nodes : a B Number of nodes : b Number of FEP : c 1.FEP proportion : c/a 2.NNS proportion : 1-|b-a|/c Circuit Similarity: 1 x 2

43. Circuit similarity matrix f g c e a b Correct implementation d Node numbers:16 f g e c Modified implementation a b d Node numbers:14 FEP:7 NNS proportion : 1- ((16-14)/16)= 14/16 FEP proportion : 7/16 Circuit Similarity:98/256= 38%

44. Outline • Introduction • Previous work • Problem description • Our method • Future work

45. Future work • May tweak our algorithm through doing experiment. • Adjust Circuit Similarity Matrix • Survey paper.