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The VAX Architecture

The VAX Architecture. CS–350–1: Computer Organization Spring 2004 William French Ahmed M. Kareem Horatiu Paul Stancu Steve Tran. Introduction. The purpose of this project is to explain how the VAX architecture works in terms with what we have learned in CS-350

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The VAX Architecture

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  1. The VAX Architecture CS–350–1: Computer Organization Spring 2004 William French Ahmed M. Kareem Horatiu Paul Stancu Steve Tran

  2. Introduction The purpose of this project is to explain how the VAX architecture works in terms with what we have learned in CS-350 • On October 25, 1977, the VAX was introduced by the Digital Equipment Corporation as the fist 32-bit machine available, which was designed from the ground up • VAX originally stood for Virtual Address eXtension • The VAX design was set to create an architecture that would work compatibly with all members of the VAX family.

  3. Introduction Continued • The following are some of the goals achieved by the VAX architecture: • The VAX architecture has maximal compatibility with its predecessor the PDP-11. • Shares the same byte addressing • Similar format for peripheral I/O devices and interrupt structures. • Identical data formats. • Similar assembly language format. • The VAX has extended the PDP-11’s virtual address space to a 32-bit virtual address. • The VAX has improved bit efficiency due to its wide range of data types and new addressing modes. • The VAX has an instruction set that can be extended with new data types and operators consistently with the already defined data types and operators. • The VAX has a well designed instruction set together with its operators, data types, and addressing modes, which makes it easily useable by high level languages. • The VAX system presents the customer with a wide range of options and prices.

  4. Overview of the VAX Architecture • The VAX processor contains 32-bit general-purpose registers that are used for temporary address and data storage. • VAX machines have a special internal bus design that must completely match the VAX architecture specifications in addressing. • VAX general purpose registers, from Open VMS Debugger Manual are on the right.

  5. VAX Data Types • The VAX computer is a byte addressable machine • It’s architecture has a wide range of data types

  6. Instruction Formats and Addressing Modes • Instructions in the VAX-11 instruction set are variable length • All instructions have a one byte opcode, followed by an operand specifier for each operand • Operand specifiers consist of a mode byte describing the addressing mode and general register being used, and zero or more bytes containing additional information • The mode byte is broken into two fields: a four-bit mode specifier and a four-bit register designator. • Each instruction has a fixed number of operands, although different instructions have from zero to six operands • The VAX-11 supports sixteen addressing modes

  7. Addressing Modes Lengthrefers to the length of the operand c(X) is the contents of X

  8. Literal: • values are found in the instruction • modes 0, 1, 2, 3 - syntax S^#nnn, integers in the range 0..63, inclusive • mode 8 - syntax I^#nnn, integers outside the range 0..63 • cannot be used as destination operands Register: • Rn - the data to be manipulated will be found in the specified register, rather than in memory • Register deferred mode (Rn) - the specified register contains a memory address which is the actual address of the operand Autoincrement / Autodecrement: • (Rn)+ and -(Rn) combine the effect of register deferred mode with automatic modification of the specified register • the register is modified through the addition or subtraction of the length of the operand, in bytes Displacement: • the address of the operand is to be calculated at execution time by adding the contents of a specified register and a one-, two-, or four-byte offset value • d(Rn), d is the displacement. • range -128..127 -> byte displacement • within the range -32768..32767 ->word displacement • everything else longword displacement

  9. Indexed: a ‘‘combination’’ addressing mode • must be used in conjunction with one of the other modes, with the exception of literal mode • is specified by following the base mode with an index specifier, [Rn], in the source code • in the machine code, the index mode byte precedes the base mode byte Example: The operand (R4)+[R6] is represented as: 1. a mode byte of 46 (indexed mode on R6) 2. followed by the byte 84 (autoincrement mode on R4) The contents of the index register are scaled by multiplying them by the operand length; this product is added to the initial effective address to form the final effective address of the operand

  10. Instructions VAX Instructions can be broken down into these categories Integer Arithmetic Address Variable-Length Bit Field Control Procedure Miscellaneous Queue Floating Point Character-String Cyclic Redundancy Check Edit Common data item sizes : B = byte, W = word, L = long word

  11. A Behind the Scenes look at what’s happening Sum = addend + sum sum addend + 1 addend sum addend addend 2 addends +

  12. Floating Point Numbers Basic syntax for floating point instructions (operation) (floating point type: must be F, D, G, or H) (Number of operands: 2 or 3 only) ADDF2 ADDF3 DIVG2 ADD F_floating 2 operand ADD F_floating 3 operand Divide G_floating 2 operand Not always the case, just for educated guesses! MOVH Move H_floating

  13. Intro to Memory Management Jobs Of Memory Management: Aids in ensuring that one process does not interfere with other processes or the operating system. Provides memory access control by assigning one of four hierarchical modes. Provides the CPU with all mapping information, and maintains a table of mapping information that keep track of where each 512 byte virtual page will be located in memory. Translates virtual addresses into physical addresses, then provides memory protection. Provides a large address space known as the virtual address space.

  14. Virtual Address Space 0000 0000: 3FFF FFFF: 4000 0000: 7FFF FFFF: 8000 0000: BFFF FFFF: 0000 0000: FFFF FFFF:

  15. Virtual Address Format • Each instruction and operand in memory has 32-bit virtual address space generated by the VAX architecture. • The system translates each virtual address to a physical address as the program executes. • The virtual address consists of a region field, a virtual page field, and a byte within page field as shown below: 313029 98 0

  16. Memory Protection • Memory protection is the process of validation whether a particular type of memory access is to be allowed on a certain page. • There are several access modes: Kernel, Executive, Supervisor, and User. • The system space is shared, but a program may be prevented from changing or even reading portions of the address. • The contents of the length register are associated within in the region P0LR, P1LR, or SLR • If any illegal address is attempted by either a length violation or an invalid protection code, an access-control-violation occurs.

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