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CS433: Computer System Organization

This lecture provides insights into the TigerSHARC processor architecture, focusing on hardware organization and programming aspects. Key topics include memory-mapped universal registers, ALU operations (arithmetic, logical, floating-point), and instruction encoding methodologies. Emphasis is placed on the processor's capabilities in complex arithmetic and its data handling capabilities. Additionally, it invites students to share their thoughts on homework, quizzes, and overall course impressions, facilitating an interactive learning environment.

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CS433: Computer System Organization

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  1. CS433: Computer System Organization Luddy Harrison ADI TigerSHARC

  2. Questions? • Questions about HW? • Impressions of last quiz? • Other comments? • You can send me email if you prefer.

  3. Note on Figures • The figures in this lecture are taken from the Analog Devices Hardware and Programming References for the TigerSHARC 201.

  4. Processor Core

  5. Processor Peripherals

  6. Uniprocessor Configuration

  7. Multiprocessor Configuration

  8. Memory and Busses

  9. Clock Domains

  10. Register Data Formats

  11. Instruction Line Organization

  12. Compute Block Registers

  13. X/YStat Upper Bits

  14. X/YStat Lower Bits

  15. Register Name Syntax

  16. Universal Registers • (Almost) all of the registers in the TigerSHARC are memory-mapped • The entire space of memory-mapped registers is referred to as universal registers • These are identified in instruction encodings by a group and a register number within the group

  17. 4x16 Vector Addition

  18. Instruction Summaries • These are in the TigerSHARC 201 Programmer’s Reference, Appendix A (on the web site)

  19. ALU Arithmetic

  20. ALU Arithmetic

  21. ALU Logical

  22. ALU Miscellaneous

  23. ALU Floating Point

  24. ALU Floating Point

  25. ALU Multiplier (32 bit)

  26. ALU Multiplier (quad 16-bit)

  27. ALU Multiply 32-bit Complex (Ai + B) × (Ci + D) = -AC + ADi + BCi + BD A complex multiply entails 4 real multiplies. A 32-bit complex number on TS has real and imaginary parts, each a 16-bit signed fraction. Q: Do we need special complex add instructions on TS?

  28. ALU Shifter

  29. ALU Shifter

  30. J Unit Arithmetic and Logical

  31. K Unit Arithmetic and Logical

  32. Load Data Regs • CB = circular buffer • BR = bit reversed arithmetic in address calculation • DAB = data alignment buffer • SDAB = short data alignment buffer

  33. Store Data Regs

  34. Sequencer

  35. Instruction Encoding

  36. Compute Block

  37. Fields in Standard Compute Block Insn

  38. IALU

  39. Load and Store

  40. Sequencer

  41. Link Ports

  42. Link Port Buffers

  43. Link Ports – 4 bit mode

  44. Link Ports – 1 bit mode

  45. Link Ports – TS to TS

  46. Link Port 4-bit DDR

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