variables attributes functions and procedures data types l.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Variables, Attributes, Functions and Procedures, Data Types PowerPoint Presentation
Download Presentation
Variables, Attributes, Functions and Procedures, Data Types

Loading in 2 Seconds...

play fullscreen
1 / 105

Variables, Attributes, Functions and Procedures, Data Types - PowerPoint PPT Presentation


  • 134 Views
  • Uploaded on

ECE 545 Lecture 10. Variables, Attributes, Functions and Procedures, Data Types. Resources. Volnei A. Pedroni , Circuit Design with VHDL Chapter 7, Signals and Variables Chapter 11, Functions and Procedures Sundar Rajan, Essential VHDL: RTL Synthesis Done Right

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

Variables, Attributes, Functions and Procedures, Data Types


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
resources
Resources
  • Volnei A. Pedroni,Circuit Design with VHDL
    • Chapter 7, Signals and Variables
    • Chapter 11, Functions and Procedures
  • Sundar Rajan, Essential VHDL: RTL Synthesis
  • Done Right
  • Chapter 11, Scalable and Parameterizable
  • Design
  • Chapter 12, Enhancing Design Readability
  • and Reuse

ECE 545 – Introduction to VHDL

slide3

Combinational Logic Synthesis

for

Intermediates

ECE 545 – Introduction to VHDL

2 to 4 decoder
2-to-4 Decoder

w

y

0

0

w

y

1

1

y

2

y

En

3

w

w

y

y

y

y

En

1

0

0

1

2

3

0

0

0

1

0

0

1

0

1

0

1

0

0

1

1

1

0

0

0

1

0

1

1

1

0

0

0

1

x

x

0

0

0

0

0

(a) Truth table

(b) Graphical symbol

ECE 545 – Introduction to VHDL

vhdl code for a 2 to 4 decoder
VHDL code for a 2-to-4 Decoder

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY dec2to4 IS

PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ;

y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END dec2to4 ;

ARCHITECTURE dataflow OF dec2to4 IS

SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;

BEGIN

Enw <= En & w ;

WITH Enw SELECT

y <= “0001" WHEN "100",

"0010" WHEN "101",

"0100" WHEN "110",

“1000" WHEN "111",

"0000" WHEN OTHERS ;

END dataflow ;

ECE 545 – Introduction to VHDL

describing combinational logic using processes
Describing combinational logic using processes

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY dec2to4 IS

PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ;

y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END dec2to4 ;

ARCHITECTURE Behavior OF dec2to4 IS

BEGIN

PROCESS ( w, En )

BEGIN

IF En = '1' THEN

CASE w IS

WHEN "00" => y <= "1000" ;

WHEN "01" => y <= "0100" ;

WHEN "10" => y <= "0010" ;

WHEN OTHERS => y <= "0001" ;

END CASE ;

ELSE

y <= "0000" ;

END IF ;

END PROCESS ;

END Behavior ;

ECE 545 – Introduction to VHDL

describing combinational logic using processes7
Describing combinational logic using processes

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY seg7 IS

PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;

END seg7 ;

ARCHITECTURE Behavior OF seg7 IS

BEGIN

PROCESS ( bcd )

BEGIN

CASE bcd IS -- abcdefg

WHEN "0000" => leds <= "1111110" ;

WHEN "0001" => leds <= "0110000" ;

WHEN "0010" => leds <= "1101101" ;

WHEN "0011" => leds <= "1111001" ;

WHEN "0100" => leds <= "0110011" ;

WHEN "0101" => leds <= "1011011" ;

WHEN "0110" => leds <= "1011111" ;

WHEN "0111" => leds <= "1110000" ;

WHEN "1000" => leds <= "1111111" ;

WHEN "1001" => leds <= "1110011" ;

WHEN OTHERS => leds <= "-------" ;

END CASE ;

END PROCESS ;

END Behavior ;

ECE 545 – Introduction to VHDL

describing combinational logic using processes8
Describing combinational logic using processes

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY compare1 IS

PORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;

END compare1 ;

ARCHITECTURE Behavior OF compare1 IS

BEGIN

PROCESS ( A, B )

BEGIN

AeqB <= '0' ;

IF A = B THEN

AeqB <= '1' ;

END IF ;

END PROCESS ;

END Behavior ;

ECE 545 – Introduction to VHDL

incorrect code for combinational logic implied latch 1
Incorrect code for combinational logic- Implied latch (1)

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY implied IS

PORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;

END implied ;

ARCHITECTURE Behavior OF implied IS

BEGIN

PROCESS ( A, B )

BEGIN

IF A = B THEN

AeqB <= '1' ;

END IF ;

END PROCESS ;

END Behavior ;

ECE 545 – Introduction to VHDL

incorrect code for combinational logic implied latch 2
Incorrect code for combinational logic- Implied latch (2)

A

AeqB

B

ECE 545 – Introduction to VHDL

describing combinational logic using processes11
Describing combinational logic using processes

Rules that need to be followed:

  • All inputs to the combinational circuit should be included
  • in the sensitivity list
  • No other signals should be included
  • in the sensitivity list
  • None of the statements within the process
  • should be sensitive to rising or falling edges
  • All possible cases need to be covered in the internal
  • IF and CASE statements in order to avoid
  • implied latches

ECE 545 – Introduction to VHDL

covering all cases in the if statement
Covering all cases in the IF statement

Using ELSE

IF A = B THEN

AeqB <= '1' ;

ELSE

AeqB <= '0' ;

Using default values

AeqB <= '0' ;

IF A = B THEN

AeqB <= '1' ;

ECE 545 – Introduction to VHDL

covering all cases in the case statement
Covering all cases in the CASE statement

Using WHEN OTHERS

CASE y IS

WHEN S1 => Z <= "10";

WHEN S2 => Z <= "01";

WHEN S3 => Z <= "00";

WHEN OTHERS => Z <= „--";

END CASE;

CASE y IS

WHEN S1 => Z <= "10";

WHEN S2 => Z <= "01";

WHEN OTHERS => Z <= "00";

END CASE;

Using default values

Z <= "00";

CASE y IS

WHEN S1 => Z <= "10";

WHEN S2 => Z <= "10";

END CASE;

ECE 545 – Introduction to VHDL

slide14

Combinational Logic Synthesis

for

Advanced

ECE 545 – Introduction to VHDL

advanced vhdl for synthesis
Advanced VHDL for synthesis

For complex, generic, and/or regular circuits

you may consider using

PROCESSES with internal

VARIABLES and

FOR LOOPs

ECE 545 – Introduction to VHDL

slide16

Variables

ECE 545 – Introduction to VHDL

variable example 1
Variable – Example (1)

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY Numbits IS

PORT ( X : IN STD_LOGIC_VECTOR(1 TO 3) ;

Count : OUT INTEGER RANGE 0 TO 3) ;

END Numbits ;

ECE 545 – Introduction to VHDL

variable example 2
Variable – Example (2)

ARCHITECTURE Behavior OF Numbits IS

BEGIN

PROCESS(X) – count the number of bits in X equal to 1

VARIABLE Tmp: INTEGER;

BEGIN

Tmp := 0;

FOR i IN 1 TO 3 LOOP

IF X(i) = ‘1’ THEN

Tmp := Tmp + 1;

END IF;

END LOOP;

Count <= Tmp;

END PROCESS;

END Behavior ;

ECE 545 – Introduction to VHDL

variables features
Variables - features
  • Can only be declared within processes and subprograms (functions & procedures)
  • Initial value can be explicitly specified in the declaration
  • When assigned take an assigned value immediately
  • Variable assignments represent the desired behavior, not the structure of the circuit
  • Should be avoided, or at least used with caution in a synthesizable code

ECE 545 – Introduction to VHDL

slide20

Variables vs. Signals

ECE 545 – Introduction to VHDL

variable example
Variable – Example

ARCHITECTURE Behavior OF Numbits IS

BEGIN

PROCESS(X) – count the number of bits in X equal to 1

VARIABLE Tmp: INTEGER;

BEGIN

Tmp := 0;

FOR i IN 1 TO 3 LOOP

IF X(i) = ‘1’ THEN

Tmp := Tmp + 1;

END IF;

END LOOP;

Count <= Tmp;

END PROCESS;

END Behavior ;

ECE 545 – Introduction to VHDL

incorrect code using signals
Incorrect Code using Signals

ARCHITECTURE Behavior OF Numbits IS

SIGNAL Tmp : INTEGER RANGE 0 TO 3 ;

BEGIN

PROCESS(X) – count the number of bits in X equal to 1

BEGIN

Tmp <= 0;

FOR i IN 1 TO 3 LOOP

IF X(i) = ‘1’ THEN

Tmp <= Tmp + 1;

END IF;

END LOOP;

Count <= Tmp;

END PROCESS;

END Behavior ;

ECE 545 – Introduction to VHDL

n bit nand
N-bit NAND

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY NANDn IS

GENERIC (n: INTEGER := 8)

PORT ( X : IN STD_LOGIC_VECTOR(1 TO n);

Y : OUT STD_LOGIC);

END NANDn;

ECE 545 – Introduction to VHDL

n bit nand architecture using variables
N-bit NAND architecture using variables

ARCHITECTUREbehavioral1OFNANDnIS

BEGIN

PROCESS (X)

VARIABLETmp: STD_LOGIC;

BEGIN

Tmp:=X(1);

AND_bits: FOR i IN2TO n LOOP

Tmp:=TmpANDX( i ) ;

END LOOP AND_bits ;

Y <= NOT Tmp ;

END PROCESS;

ENDbehavioral1 ;

ECE 545 – Introduction to VHDL

incorrect n bit nand architecture using signals
Incorrect N-bit NAND architecture using signals

ARCHITECTUREbehavioral2OFNANDnIS

SIGNALTmp: STD_LOGIC;

BEGIN

PROCESS (X)

BEGIN

Tmp<= X(1);

AND_bits: FOR i IN2TO nLOOP

Tmp<= TmpANDX( i ) ;

END LOOP AND_bits ;

Y <= NOT Tmp ;

END PROCESS;

ENDbehavioral2 ;

ECE 545 – Introduction to VHDL

correct n bit nand architecture using signals
Correct N-bit NAND architecture using signals

ARCHITECTUREdataflow1 OFNANDnIS

SIGNALTmp: STD_LOGIC_VECTOR(1 TO n);

BEGIN

Tmp(1)<= X(1);

AND_bits: FOR i IN2TO n GENERATE

Tmp(i)<= Tmp(i-1)ANDX( i ) ;

END LOOP AND_bits ;

Y <= NOT Tmp(n) ;

ENDdataflow1 ;

ECE 545 – Introduction to VHDL

correct n bit nand architecture using signals27
Correct N-bit NAND architecture using signals

ARCHITECTUREdataflow2OFNANDnIS

SIGNALTmp: STD_LOGIC_VECTOR(1 TO n);

BEGIN

Tmp <= (OTHERS => 1);

Y <= ‘0’ WHEN X = Tmp ELSE ‘1’;

ENDdataflow2 ;

ECE 545 – Introduction to VHDL

parity generator entity
Parity generator entity

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY oddParityLoop IS

GENERIC ( width : INTEGER := 8 );

PORT (ad : in STD_LOGIC_VECTOR (width - 1 DOWNTO 0);

oddParity : out STD_LOGIC ) ;

END oddParityLoop ;

ECE 545 – Introduction to VHDL

parity generator architecture using signals
Parity generator architecture using signals

ARCHITECTURE dataflow OF oddParityGen IS

SIGNAL genXor: STD_LOGIC_VECTOR(width DOWNTO 0);

BEGIN

genXor(0) <= '0';

parTree: FOR i IN 1 TO width GENERATE

genXor(i) <= genXor(i - 1) XOR ad(i - 1);

END GENERATE;

oddParity <= genXor(width) ;

END dataflow ;

ECE 545 – Introduction to VHDL

parity generator architecture using variables
Parity generator architecture using variables

ARCHITECTURE behavioral OF oddParityLoop IS

BEGIN

PROCESS (ad)

VARIABLE loopXor: STD_LOGIC;

BEGIN

loopXor := '0';

FOR i IN 0 to width -1 LOOP

loopXor := loopXor XOR ad( i ) ;

END LOOP ;

oddParity <= loopXor ;

END PROCESS;

END behavioral ;

ECE 545 – Introduction to VHDL

slide31

Sequential Logic Synthesis

for

Beginners

ECE 545 – Introduction to VHDL

for beginners
For Beginners

Use processes with very simple structure only

to describe

- registers

- shift registers

- counters

- state machines.

Use examples discussed in class as a template.

Create generic entities for registers, shift registers, and

counters, and instantiate the corresponding components in

a higher level circuit using GENERIC MAP PORT MAP.

Supplement sequential components with

combinational logic described using concurrent statements.

ECE 545 – Introduction to VHDL

slide33

Sequential Logic Synthesis

for

Intermediates

ECE 545 – Introduction to VHDL

for intermmediates
For Intermmediates
  • Use Processes with IF and CASE statements only. Do not use LOOPS or VARIABLES.
  • Sensitivity list of the PROCESS should include only signals that can by themsleves change the outputs of the sequential circuit (typically, clock and asynchronous set or reset)
  • Do not use PROCESSes without sensitivity list

(they can be synthesizable, but make simulation inefficient)

ECE 545 – Introduction to VHDL

slide35

Constrained Array Types

ECE 545 – Introduction to VHDL

one dimensional arrays examples 1
One-dimensional arrays – Examples (1)

type word_asc isarray(0 to 31) of std_logic;

type word_desc is array(31 downto 0) ofstd_logic;

…..

signal buffer_register: word_desc;

…..

buffer_register(6) <= ‘1’;

…..

variable tmp : word_asc;

…..

tmp(5):= ‘0’;

ECE 545 – Introduction to VHDL

one dimensional arrays examples 2
One-dimensional arrays – Examples (2)

type controller_state is (initial, idle, active, error);

type state_counts_imp is array(idle to error) of natural;

type state_counts_exp is array(controller_state range idle to error) of natural;

type state_counts_full is array(controller_state) of natural;

…..

variable counters: state_counts_exp;

…..

counters(active) := 0;

…..

counters(active) := counters(active) + 1;

ECE 545 – Introduction to VHDL

slide38

Unconstrained Array Types

ECE 545 – Introduction to VHDL

predefined unconstrained array types
Predefined Unconstrained Array Types

Predefined

bit_vector array of bits

string array of characters

Defined in the ieee.std_logic_1164 package:

std_logic_vector array of std_logic_vectors

ECE 545 – Introduction to VHDL

predefined unconstrained array types40
Predefined Unconstrained Array Types

subtype byte is bit_vector(7 downto 0);

….

variable channel_busy : bit_vector(1 to 4);

….

constant ready_message :string := “ready”;

….

signal memory_bus: std_logic_vector (31 downto 0);

ECE 545 – Introduction to VHDL

user defined unconstrained array types
User-defined Unconstrained Array Types

type sample is array (natural range <>) of integer;

….

variable long_sample is sample(0 to 255);

….

constant look_up_table_1: sample :=

(127, -45, 63, 23, 76);

….

ECE 545 – Introduction to VHDL

slide42

Attributes of Arrays and Array Types

ECE 545 – Introduction to VHDL

array attributes
Array Attributes

A’left(N) left bound of index range of dimension N of A

A’right(N) right bound of index range of dimension N of A

A’low(N) lower bound of index range of dimension N of A

A’high(N) upper bound of index range of dimension N of A

A’range(N) index range of dimension N of A

A’reverse_range(N) reversed index range of dimension N of A

A’length(N) length of index range of dimension N of A

A’ascending(N)true if index range of dimension N of A

is an ascending range, false otherwise

ECE 545 – Introduction to VHDL

array attributes examples
Array Attributes - Examples

type A is array (1 to 4, 31 downto 0);

A’left(1) = 1

A’right(2) = 0

A’low(1) = 1

A’high(2) = 31

A’range(1) = 1 to 4

A’length(2) = 32

A’ascending(2) = false

ECE 545 – Introduction to VHDL

slide45

Subprograms

ECE 545 – Introduction to VHDL

subprograms
Subprograms
  • Include

functions and procedures

  • Commonly used pieces of code
  • Can be placed in a library, and then reused and shared among various projects
  • Abstract operations that are repeatedly performed
  • Type conversions
  • Use only sequential statements, the same as processes

ECE 545 – Introduction to VHDL

typical locations of subprograms
Typical locations of subprograms

PACKAGE

PACKAGE BODY

LIBRARY

global

ENTITY

FUNCTION /

PROCEDURE

local for all architectures

of a given entity

ARCHITECTURE

Declarative part

local for a given architecture

ECE 545 – Introduction to VHDL

slide48

Functions

ECE 545 – Introduction to VHDL

functions basic features
Functions – basic features

Functions

  • always return a single value as a result
  • Are called using formal and actual parametersthe same way as components
  • never modify parameters passed to them
  • parameters can only be constants (including generics) and signals (including ports);

variables are not allowed; the default is a CONSTANT

  • when passing parameters, no range specification should be included (for example no RANGE for INTEGERS, or TO/DOWNTO for STD_LOGIC_VECTOR)
  • are always used in some expression, and not called on their own

ECE 545 – Introduction to VHDL

function syntax
Function syntax

FUNCTION function_name (<parameter_list>)

RETURN data_type IS

[declarations]

BEGIN

(sequential statements)

END function_name;

ECE 545 – Introduction to VHDL

function parameters example
Function parameters - example

FUNCTION f1

(a, b: INTEGER; SIGNAL c: STD_LOGIC_VECTOR)

RETURN BOOLEAN IS

BEGIN

(sequantial statements)

END f1;

ECE 545 – Introduction to VHDL

function calls examples
Function calls - examples

x <= conv_integer(a);

IF x > maximum(a, b) THEN ....

WHILE minimum(a, b) LOOP

.......

ECE 545 – Introduction to VHDL

function example 1
Function – Example 1

LIBRARY ieee;

USE ieee.std_logic_1164.all;

PACKAGE my_package IS

FUNCTION log2_ceil (CONSTANT s: INTEGER) RETURN INTEGER;

END my_package;

PACKAGE body my_package IS

FUNCTION log2_ceil (CONSTANT s: INTEGER) RETURN INTEGER IS

VARIABLE m,n : INTEGER;

BEGIN

m := 0;

n := 1;

WHILE (n < s) LOOP

m := m + 1;

n := n*2;

END LOOP;

RETURN m;

END log2_ceil;

END my_package;

ECE 545 – Introduction to VHDL

function call example 1
Function call – Example 1

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

USE work.my_package.all;

ENTITY log2_int IS

GENERIC (m: INTEGER :=20);

PORT (x: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END log2_int;

ARCHITECTURE log2_int OF log2_int IS

CONSTANT l2m : INTEGER := log2_ceil (m);

SIGNAL r : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

r <= conv_std_logic_vector(l2m,4);

y <= x*r;

END log2_int;

ECE 545 – Introduction to VHDL

function e xample 2
Function – Example 2

library IEEE;

use IEEE.std_logic_1164.all;

ENTITY powerOfFour IS

PORT(

X : IN INTEGER;

Y : OUT INTEGER;

);

END powerOfFour;

ECE 545 – Introduction to VHDL

function e xample 256
Function – Example 2

ARCHITECTURE behavioral OF powerOfFour IS

FUNCTION Pow ( SIGNAL N:INTEGER; Exp : INTEGER) RETURNINTEGERIS

VARIABLE Result : INTEGER := 1;

BEGIN

FOR i IN 1 TO Exp LOOP

Result := Result * N;

END LOOP;

RETURN( Result );

END Pow;

BEGIN

Y <= Pow(X, 4);

END behavioral;

ECE 545 – Introduction to VHDL

package containing a function 1
Package containing a function (1)

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

PACKAGE specialFunctions IS

FUNCTION Pow( SIGNAL N: INTEGER; Exp : INTEGER) RETURNINTEGER;

END specialFunctions

ECE 545 – Introduction to VHDL

package containing a function 2
Package containing a function (2)

PACKAGE BODY specialFunctions IS

FUNCTION Pow(SIGNAL N: INTEGER; Exp : INTEGER)

RETURNINTEGERIS

VARIABLE Result : INTEGER := 1;

BEGIN

FOR i IN 1 TO Exp LOOP

Result := Result * N;

END LOOP;

RETURN( Result );

END Pow;

END specialFunctions

ECE 545 – Introduction to VHDL

type conversion function 1
Type conversion function (1)

LIBRARY ieee;

USE ieee.std_logic_1164.all;

-------------------------------------------------------------------------------------------------

PACKAGE my_package IS

FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR)

RETURN INTEGER;

END my_package;

-------------------------------------------------------------------------------------------------

ECE 545 – Introduction to VHDL

type conversion function 2
Type conversion function (2)

PACKAGE BODY my_package IS

FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR)

RETURN INTEGER;

VARIABLE result: INTEGER RANGE 0 TO 2**vector’LENGTH - 1;

VARIABLE carry: STD_LOGIC;

BEGIN

IF(vector(vector’HIGH)=‘1’ THEN result:=1;

ELSE result := 0;

FOR i IN (vector’HIGH-1) DOWNTO (vector’LOW) LOOP

result := result*2;

IF (vector(i) = ‘1’) THEN result := result+1;

END IF;

RETURN result;

END conv_integer;

END my_package;

ECE 545 – Introduction to VHDL

type conversion function 3
Type conversion function (3)

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.my_package.all;

-------------------------------------------------------------------------------------------------

ENTITY conv_int2 IS

PORT ( a: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

y: OUT INTEGER RANGE 0 TO 15);

END conv_int2;

-------------------------------------------------------------------------------------------------

ARCHITECTURE my_arch OF conv_int2 IS

BEGIN

y <= conv_integer(a);

END my_arch;

ECE 545 – Introduction to VHDL

slide62

Procedures

ECE 545 – Introduction to VHDL

procedures basic features
Procedures – basic features

Procedures

  • do not return a value
  • are called using formal and actual parametersthe same way as components
  • may modify parameters passed to them
  • each parameter must have a mode: IN, OUT, INOUT
  • parameters can be constants (including generics), signals (including ports), and variables;the default for inputs (mode in) is a constant, the default for outputs (modes out and inout) is a variable
  • when passing parameters, range specification should be included (for example RANGE for INTEGERS, and TO/DOWNTO for STD_LOGIC_VECTOR)
  • Procedure calls are statements on their own

ECE 545 – Introduction to VHDL

procedure syntax
Procedure syntax

PROCEDURE procedure_name (<parameter_list>) IS

[declarations]

BEGIN

(sequential statements)

END function_name;

ECE 545 – Introduction to VHDL

procedure parameters example
Procedure parameters - example

FUNCTION f1

(a, b: INTEGER; SIGNAL c: STD_LOGIC_VECTOR)

RETURN BOOLEAN IS

BEGIN

(sequantial statements)

END f1;

ECE 545 – Introduction to VHDL

procedure calls examples
Procedure calls - examples

compute_min_max(in1, in2, in3, out1, out2);

divide(dividend, divisor, quotient, remainder);

IF (a > b) THEN

compute_min_max(in1, in2, in3, out1, out2);

.......

ECE 545 – Introduction to VHDL

procedure example 1
Procedure – example (1)

LIBRARYieee;

USEieee.std_logic_1164.all;

USE work.decProcs.all;

ENTITY decoder IS port (

decIn: INSTD_LOGIC_VECTOR(1 DOWNTO 0);

decOut: OUTSTD_LOGIC_VECTOR(3 DOWNTO 0)

);

END decoder;

ECE 545 – Introduction to VHDL

procedure example 2
Procedure – example (2)

ARCHITECTURE simple OF decoder IS

PROCEDURE DEC2x4 (inputs : in STD_LOGIC_VECTOR(1 downto 0);

decode: out STD_LOGIC_VECTOR(3 downto 0)

) IS

BEGIN

CASE inputs IS

WHEN "11" =>

decode := "1000";

WHEN "10" =>

decode := "0100";

WHEN "01" =>

decode := "0010";

WHEN "00" =>

decode := "0001";

WHEN others =>

decode := "0001";

END case;

END DEC2x4;

BEGIN

DEC2x4(decIn,decOut);

END simple;

ECE 545 – Introduction to VHDL

slide69

Operators

ECE 545 – Introduction to VHDL

operator as a function 1
Operator as a function (1)

LIBRARY ieee;

USE ieee.std_logic_1164.al;

-------------------------------------------------------------------------------------------------

PACKAGE my_package IS

FUNCTION "+" (a, b: STD_LOGIC_VECTOR)

RETURN STD_LOGIC_VECTOR;

END my_package;

-------------------------------------------------------------------------------------------------

ECE 545 – Introduction to VHDL

operator as a function 2
Operator as a function (2)

PACKAGE BODY my_package IS

FUNCTION "+" (a, b: STD_LOGIC_VECTOR)

RETURN STD_LOGIC_VECTOR;

VARIABLE result: STD_LOGIC_VECTOR;

VARIABLE carry: STD_LOGIC;

BEGIN

carry := ‘0’;

FOR i IN a’REVERSE_RANGE LOOP

result(i) := a(i) XOR b(i) XOR carry;

carry := (a(i) AND b(i)) OR (a(i) AND carry) OR (b(i) AND carry));

END LOOP;

RETURN result;

END "+" ;

END my_package;

ECE 545 – Introduction to VHDL

slide72

Operator Overloading

ECE 545 – Introduction to VHDL

operator overloading
Operator overloading
  • Operator overloading allows different argument types for a given operation (function)
  • The VHDL tools resolve which of these functions to select based on the types of the inputs
  • This selection is transparent to the user as long as the function has been defined for the given argument types.

ECE 545 – Introduction to VHDL

different declarations for the same operator example
Different declarations for the same operator - Example

Declarations in the package ieee.std_logic_unsigned:

function “+” ( L: std_logic_vector; R:std_logic_vector) return std_logic_vector;

function “+” ( L: std_logic_vector; R: integer) return std_logic_vector;

function “+” ( L: std_logic_vector; R:std_logic) return std_logic_vector;

ECE 545 – Introduction to VHDL

different declarations for the same operator example75
Different declarations for the same operator - Example

signal count: std_logic_vector(7 downto 0);

You can use:

count <= count + “0000_0001”;

or

count <= count + 1;

or

count <= count + ‘1’;

ECE 545 – Introduction to VHDL

slide76

VHDL as a Strongly Typed Language

ECE 545 – Introduction to VHDL

notion of type
Notion of type
  • Type defines a set of values and a set of applicable operations
  • Declaration of a type determines which values can be stored in an object (signal, variable, constant) of a given type
  • Every object can only assume values of its nominated type
  • Each operation (e.g., and, +, *) includes the types of values to which the operation may be applied, and the type of the result
  • The goal of strong typing is a detection of errors at an early stage of the design process

ECE 545 – Introduction to VHDL

example of strong typing
Example of strong typing

architecture incorrect of example1 is

type apples is range 0 to 100;

type oranges is range 0 to 100;

signal apple1: apples;

signal orange1: oranges;

begin

apple1 <= orange1;

end incorrect;

ECE 545 – Introduction to VHDL

slide79

Type Classification

ECE 545 – Introduction to VHDL

classification of data types
Classification of data types

ECE 545 – Introduction to VHDL

slide81

Integer Types

ECE 545 – Introduction to VHDL

integer type
Integer type

Name:integer

Status: predefined

Contents: all integer numbers representable on a particular host computer, but at least numbers in the range

–(231-1) .. 231-1

ECE 545 – Introduction to VHDL

user defined integer types examples
User defined integer types - Examples

type day_of_month is range 0 to 31;

type year is range 0 to 2100;

type set_index_range is range 999 downto 100;

constant number_of_bits: integer :=32;

type bit_index is range 0 to number_of_bits-1;

Values of bounds can be expressions, but

need to be known when the model is analyzed.

ECE 545 – Introduction to VHDL

slide84

Enumeration Types

ECE 545 – Introduction to VHDL

predefined enumeration types 1
Predefined enumeration types (1)

boolean (true, false)

bit (‘0’, ‘1’)

characterVHDL-87:

128 7-bit ASCII characters

VHDL-93:

256 ISO 8859 Latin-1 8-bit characters

ECE 545 – Introduction to VHDL

predefined enumeration types 2
Predefined enumeration types (2)

severity_level (note, warning, error, failure)

Predefined in VHDL-93 only:

file_open_kind

(read_mode, write_mode, append_mode)

file_open_status

(open_ok, status_error, name_error, mode_error)

ECE 545 – Introduction to VHDL

user defined enumeration types examples
User-defined enumeration types - Examples

type state is (S0, S1);

type alu_function is (disable, pass, add, subtract,

multiply, divide);

type octal_digit is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’);

type mixed is (lf, cr, ht, ‘-’, ‘/‘, ‘\’);

Each value in an enumeration type must be either

an identifier or a character literal

ECE 545 – Introduction to VHDL

slide88

Floating-Point Types

ECE 545 – Introduction to VHDL

floating point types
Floating point types
  • Used to represent real numbers
  • Numbers are represented using a significand (mantissa) part and an exponent part
  • Conform to the IEEE standard 754 or 854

Minimum size of representation that must be

supported by the implementation of the VHDL

standard:

VHDL-2001: 64-bit representation

VHDL-87, VHDL-93: 32-bit representation

ECE 545 – Introduction to VHDL

real literals examples
Real literals - examples

23.1 23.1

46E5 46  105

1E+12 1  1012

1.234E09 1.234  109

34.0e-08 34.0  10-8

2#0.101#E5 0.1012  25 =(2-1+2-3)  25

8#0.4#E-6 0.48  8-6 = (4  8-1)  8-6

16#0.a5#E-8 0.a516  16-8 =(1016-1+516-2)  16-8

ECE 545 – Introduction to VHDL

the ansi ieee standard floating point number representation formats
The ANSI/IEEE standard floating-point number representation formats

ECE 545 – Introduction to VHDL

user defined floating point types examples
User-defined floating-point types - Examples

type input_level is range -10.0 to +10.0

type probability is range 0.0 to 1.0;

constant max_output: real := 1.0E6;

constant min_output: real := 1.0E-6;

type output_range is max_output downto min_output;

ECE 545 – Introduction to VHDL

slide93

Attributes of Scalar Types

ECE 545 – Introduction to VHDL

attributes of all scalar types
Attributes of all scalar types

T’left first (leftmost) value in T

T’right last (rightmost) value in T

T’low least value in T

T’high greatest value in T

Not available in VHDL-87:

T’ascending

true if T is an ascending range, false otherwise

T’image(x) a string representing the value of x

T’value(s) the value in T that is represented by s

ECE 545 – Introduction to VHDL

attributes of all scalar types examples
Attributes of all scalar types - examples

type index_range is range 21 downto 11;

index_range’left = 21

index_range’right = 11

index_range’low = 11

index_range’high = 21

index_range’ascending = false

index_range’image(14) = “14”

index_range’value(“20”) = 20

ECE 545 – Introduction to VHDL

attributes of discrete types
Attributes of discrete types

T’pos(x) position number of x in T

T’val(n) value in T at position n

T’succ(x) value in T at position one greater than position of x

T’pred(x) value in T at position one less than position of x

T’leftof(x) value in T at position one to the left of x

T’rightof(x) value in T at position one to the right of x

ECE 545 – Introduction to VHDL

attributes of discrete types examples
Attributes of discrete types - examples

type logic_level is (unknown, low, undriven, high);

logic_level’pos(unknown) = 0

logic_level’val(3) = high

logic_level’succ(unknown) = low

logic_level’pred(undriven) = low

logic_level’leftof(unknown) error

logic_level’rightof(undriven) = high

ECE 545 – Introduction to VHDL

slide98

Subtypes

ECE 545 – Introduction to VHDL

subtype
Subtype
  • Defines a subset of a base type values
  • A condition that is used to determine which values are included in the subtype is called a constraint
  • All operations that are applicable to the base type also apply to any of its subtypes
  • Base type and subtype can be mixed in the operations, but the result must belong to the subtype, otherwise an error is generated.

ECE 545 – Introduction to VHDL

predefined subtypes
Predefined subtypes

natural integers  0

positive integers > 0

Not predefined in VHDL-87:

delay_length time  0

ECE 545 – Introduction to VHDL

user defined subtypes examples
User-defined subtypes - Examples

subtype bit_index is integer range 31 downto 0;

subtype input_range is real range 1.0E-9 to 1.0E+12;

ECE 545 – Introduction to VHDL

slide102

Operators

ECE 545 – Introduction to VHDL

operators 1
Operators (1)

ECE 545 – Introduction to VHDL

operators 2
Operators (2)

ECE 545 – Introduction to VHDL

operators 3
Operators (3)

ECE 545 – Introduction to VHDL