Practical Design Guidelines Gord Allan PhD Candidate Wireless ASICs

1. Practical Design GuidelinesGord AllanPhD CandidateWireless ASICs • K.I.S.S.- fewer lines leave less places to go wrong- don’t use a trick to save 2 flops in a 1M gate design if readability suffers- De-Risk everywhere!- The simpler the design is to understand the easier it is to verify.- Think about HW first – then code based on that. • Separate Sequential and Combinational Processes.- Either: always @(edge clk or edge reset) DON’T OR always @(every input in block) MIX - use assign statements for simple combinational logic. • Latches are evil.- create races/hazards, are un-testable, are not wanted- to avoid – cover all cases in C/L and include all inputs in sensitivity list • To Block (=) or not to Block (<=).- Use non-blocking assignment (<=) in all flops- Why? Because that’s how HW behaves – samples at clk edge. • Never use initial assignments in HW code.- (eg. reg [2:0]state = 3’b000;) • Modularity (back to KISS) - a block should be as simple and ‘dumb’ as possible.- a module should do only it’s job - nothing else.- in large projects the ‘boundaries’ will otherwise get confused. • Verification – proper test-benches- don’t change inputs on clk edges- rarely useful to go searching through waveforms- code is always in a state of ‘flux’- need automated test information, self-checking test-benches!- normally event driven (eg. wait (signal==0); …)- never let code ‘out-the door’ before you are SURE it works!