Xc9500xl - PowerPoint PPT Presentation

XC9500XL Architecture

XC9500XL Architecture. CPLD Product Applications. TIB_archB1. XC9500XL Overview. Superset of XC9500 CPLD Optimized for 3.3V systems compatible levels with 5.0/2.5V High f MAX = 200 MHz Fast t PD = 4 nsec Best ISP/JTAG support Best pinlocking Advanced Packaging. Agenda. Overview

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Xilinx XC9500 CPLDs

Xilinx XC9500 CPLDs. 125MHz. XC9500. XC9500XL Key Features. 200MHz. High performance t PD = 5ns, f SYS = 178MHz 36 to 288 macrocell densities Lowest price, best value CPLD Highest programming reliability Most complete IEEE 1149.1 JTAG

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269 views • 14 slides

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