'Rclk' presentation slideshows

Status report

Status report. 2011/2/4 Atsushi Nukariya. Progress. ? Progresses are as follows. 1. I created wave form which Fusayasu-san showed. ? Rearrange design. ? Change clock frequency. ? Add another clock. 2. Chip test. 3. I created function which resets FPGA and Chip.

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