Accuracy-Configurable Adder for Approximate Arithmetic Designs. Andrew B. Kahng, Seokhyeong Kang VLSI CAD LABORATORY, UC San Diego 49 th Design Automation Conference June 6 th , 2012. Outline. Background and Motivation Accuracy Configurable Adder Design Experimental Setup and ResultsBy shaw
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Adders. Used to perform addition, subtraction, multiplication, and division (sometimes) Half-adder adds rightmost ( least significant ) bit Full-adder adds all other bits, since a 1 may be carried into it. Use carry-out from one adder as the carry-in for the next adder
Adders. Adders. Basic Ripple Adders Faster Adders Sequential Adders. The Half Adder. Half Adder Input is limited to 2 bits HS = X xor Y = Xâ€¢Yâ€™ + Xâ€™â€¢Y CO = Xâ€¢Y Time for the Half Adder? 1 gate delay A gate delay of an xor for the half sum
Adders. Binary Adders. Arithmetic circuit Addition Subtraction Division Multiplication. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10. One bit in sum. Two bit in sum. Half Adder. A combinational circuit that performs the addition of two bits. Two inputs and two outputs.
Adders. Adders. Basic Ripple Adders Faster Adders Sequential Adders. The Half Adder. Half Adder Input is limited to 2 bits HS = X xor Y = X•Y’ + X’•Y CO = X•Y Time for the Half Adder? 1 gate delay A gate delay of an xor for the half sum
Adders. Full adder. 4-bit ripple adder. Subtractor from adder. Carry look-ahead adder. Previous inputs are in this logic here to speed – up the carry propagation. 74x283 4-bit binary adder. G and P bits go to all previous bits. 74x283 4-bit binary adder.
Adders. Building an Adder. The Boolean operations can be built electronically using transistors. Applying an electrical current to a terminal is the equivalent to 1 or True . No current means 0 or False .
Adders. Full-Adder. The Binary Adder. Express Sum and Carry as a function of P, G, D. Define 3 new variable which ONLY depend on A, B. Generate (G) = AB. Propagate (P) = A. B. Å. Delete =. A. B. S. C. D and P. Can also derive expressions for. and. based on. o.
Adders. Lecture L7.1 Section 7.1. Adders. Half Adder Full Adder TTL Adder. A . 0 . S . 0 . B . 0 . C . 1 . Half Adder. A . B . S . C . 0 . 0 . 0 . 1 . 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1. Dec Binary 1 1 +1 +1 2 10. Multiple-bit Addition.
Lecture 7 Carry look ahead adders, Latches, Flip-flops, registers, multiplexors, decoders Digital Works intro PH 3 : Appendix B.6-9. Adders. Last time we developed a 32 bit ripple adder. It is not an efficient adder, although simple to understand, so how can we improve its performance.