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Architecture-Level Synthesis for Automatic Interconnect Pipelining

Architecture-Level Synthesis for Automatic Interconnect Pipelining. Jason Cong, Yiping Fan , Zhiru Zhang VLSI CAD Lab Computer Science Department University of California, Los Angeles {cong, fanyp, zhiruz}@cs.ucla.edu. Funded by GSRC, NSF, and Altera Corp. Outline. Motivation

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Architecture-Level Synthesis for Automatic Interconnect Pipelining